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StackSlotColoring: Decide colors per stack ID
I thought I fixed this in r308673, but that fix was very broken. The assumption that any frame index can be used in place of another was more widespread than I realized. Even when stack slot sharing was disabled, this was still replacing frame index uses with a different ID with a different stack slot. Really fix this by doing the coloring per-stack ID, so all of the coloring logically done in a separate namespace. This is a lot simpler than trying to figure out how to change the color if the stack ID is different. llvm-svn: 335488
This commit is contained in:
Matt Arsenault
parent
69747dd448
commit
eb4c18e5a7
@ -123,6 +123,9 @@ class MachineFrameInfo {
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/// necessarily reside in the same contiguous memory block as other stack
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/// objects. Objects with differing stack IDs should not be merged or
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/// replaced substituted for each other.
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//
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/// It is assumed a target uses consecutive, increasing stack IDs starting
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/// from 1.
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uint8_t StackID;
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/// If this stack object is originated from an Alloca instruction
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@ -82,14 +82,14 @@ namespace {
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// AllColors - If index is set, it's a spill slot, i.e. color.
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// FIXME: This assumes PEI locate spill slot with smaller indices
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// closest to stack pointer / frame pointer. Therefore, smaller
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// index == better color.
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BitVector AllColors;
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// index == better color. This is per stack ID.
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SmallVector<BitVector, 2> AllColors;
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// NextColor - Next "color" that's not yet used.
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int NextColor = -1;
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// NextColor - Next "color" that's not yet used. This is per stack ID.
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SmallVector<int, 2> NextColors = { -1 };
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// UsedColors - "Colors" that have been assigned.
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BitVector UsedColors;
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// UsedColors - "Colors" that have been assigned. This is per stack ID
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SmallVector<BitVector, 2> UsedColors;
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// Assignments - Color to intervals mapping.
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SmallVector<SmallVector<LiveInterval*,4>, 16> Assignments;
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@ -196,10 +196,15 @@ void StackSlotColoring::ScanForSpillSlotRefs(MachineFunction &MF) {
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/// to a sorted (by weight) list.
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void StackSlotColoring::InitializeSlots() {
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int LastFI = MFI->getObjectIndexEnd();
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// There is always at least one stack ID.
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AllColors.resize(1);
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UsedColors.resize(1);
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OrigAlignments.resize(LastFI);
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OrigSizes.resize(LastFI);
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AllColors.resize(LastFI);
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UsedColors.resize(LastFI);
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AllColors[0].resize(LastFI);
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UsedColors[0].resize(LastFI);
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Assignments.resize(LastFI);
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using Pair = std::iterator_traits<LiveStacks::iterator>::value_type;
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@ -220,18 +225,31 @@ void StackSlotColoring::InitializeSlots() {
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int FI = TargetRegisterInfo::stackSlot2Index(li.reg);
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if (MFI->isDeadObjectIndex(FI))
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continue;
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SSIntervals.push_back(&li);
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OrigAlignments[FI] = MFI->getObjectAlignment(FI);
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OrigSizes[FI] = MFI->getObjectSize(FI);
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AllColors.set(FI);
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auto StackID = MFI->getStackID(FI);
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if (StackID != 0) {
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AllColors.resize(StackID + 1);
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UsedColors.resize(StackID + 1);
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AllColors[StackID].resize(LastFI);
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UsedColors[StackID].resize(LastFI);
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}
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AllColors[StackID].set(FI);
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}
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LLVM_DEBUG(dbgs() << '\n');
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// Sort them by weight.
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std::stable_sort(SSIntervals.begin(), SSIntervals.end(), IntervalSorter());
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NextColors.resize(AllColors.size());
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// Get first "color".
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NextColor = AllColors.find_first();
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for (unsigned I = 0, E = AllColors.size(); I != E; ++I)
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NextColors[I] = AllColors[I].find_first();
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}
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/// OverlapWithAssignments - Return true if LiveInterval overlaps with any
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@ -252,17 +270,19 @@ int StackSlotColoring::ColorSlot(LiveInterval *li) {
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int Color = -1;
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bool Share = false;
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int FI = TargetRegisterInfo::stackSlot2Index(li->reg);
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uint8_t StackID = MFI->getStackID(FI);
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if (!DisableSharing) {
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// Check if it's possible to reuse any of the used colors.
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Color = UsedColors.find_first();
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Color = UsedColors[StackID].find_first();
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while (Color != -1) {
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if (!OverlapWithAssignments(li, Color)) {
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Share = true;
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++NumEliminated;
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break;
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}
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Color = UsedColors.find_next(Color);
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Color = UsedColors[StackID].find_next(Color);
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}
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}
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@ -274,12 +294,14 @@ int StackSlotColoring::ColorSlot(LiveInterval *li) {
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// Assign it to the first available color (assumed to be the best) if it's
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// not possible to share a used color with other objects.
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if (!Share) {
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assert(NextColor != -1 && "No more spill slots?");
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Color = NextColor;
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UsedColors.set(Color);
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NextColor = AllColors.find_next(NextColor);
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assert(NextColors[StackID] != -1 && "No more spill slots?");
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Color = NextColors[StackID];
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UsedColors[StackID].set(Color);
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NextColors[StackID] = AllColors[StackID].find_next(NextColors[StackID]);
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}
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assert(MFI->getStackID(Color) == MFI->getStackID(FI));
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// Record the assignment.
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Assignments[Color].push_back(li);
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LLVM_DEBUG(dbgs() << "Assigning fi#" << FI << " to fi#" << Color << "\n");
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@ -357,11 +379,13 @@ bool StackSlotColoring::ColorSlots(MachineFunction &MF) {
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}
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// Delete unused stack slots.
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while (NextColor != -1) {
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LLVM_DEBUG(dbgs() << "Removing unused stack object fi#" << NextColor
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<< "\n");
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MFI->RemoveStackObject(NextColor);
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NextColor = AllColors.find_next(NextColor);
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for (int StackID = 0, E = AllColors.size(); StackID != E; ++StackID) {
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int NextColor = NextColors[StackID];
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while (NextColor != -1) {
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LLVM_DEBUG(dbgs() << "Removing unused stack object fi#" << NextColor << "\n");
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MFI->RemoveStackObject(NextColor);
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NextColor = AllColors[StackID].find_next(NextColor);
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}
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}
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return true;
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@ -383,6 +407,8 @@ void StackSlotColoring::RewriteInstruction(MachineInstr &MI,
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int NewFI = SlotMapping[OldFI];
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if (NewFI == -1 || NewFI == OldFI)
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continue;
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assert(MFI->getStackID(OldFI) == MFI->getStackID(NewFI));
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MO.setIndex(NewFI);
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}
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@ -487,7 +513,9 @@ bool StackSlotColoring::runOnMachineFunction(MachineFunction &MF) {
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InitializeSlots();
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Changed = ColorSlots(MF);
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NextColor = -1;
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for (int &Next : NextColors)
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Next = -1;
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SSIntervals.clear();
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for (unsigned i = 0, e = SSRefs.size(); i != e; ++i)
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SSRefs[i].clear();
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97
test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
Normal file
97
test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
Normal file
@ -0,0 +1,97 @@
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stress-regalloc=3 -start-before=greedy -stop-after=stack-slot-coloring -o - %s | FileCheck -check-prefixes=SHARE,GCN %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stress-regalloc=3 -start-before=greedy -stop-after=stack-slot-coloring -no-stack-slot-sharing -o - %s | FileCheck -check-prefixes=NOSHARE,GCN %s
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# Make sure that stack slot coloring doesn't try to merge frame
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# indexes used for SGPR spilling with those that aren't.
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# Even when stack slot sharing was disabled, it was still moving the
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# FI ID used for an SGPR spill to a normal frame index.
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--- |
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define void @sgpr_spill_wrong_stack_id(float addrspace(1)* nocapture readnone %arg, float addrspace(1)* noalias %arg1) {
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bb:
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%tmp = load i32, i32 addrspace(1)* null, align 4
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call void @func(i32 undef)
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call void @func(i32 %tmp)
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unreachable
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}
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declare void @func(i32)
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...
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---
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# GCN-LABEL: name: sgpr_spill_wrong_stack_id
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# SHARE: stack:
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# SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
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# SHARE: stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
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# SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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# SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
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# SHARE: stack-id: 1, callee-saved-register: '', callee-saved-restored: true,
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# SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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# SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
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# SHARE: stack-id: 1, callee-saved-register: '', callee-saved-restored: true,
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# SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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# SHARE: SI_SPILL_S32_SAVE $sgpr5, %stack.2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (store 4 into %stack.2, addrspace 5)
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# SHARE: SI_SPILL_V32_SAVE killed $vgpr0, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (store 4 into %stack.0, addrspace 5)
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# SHARE: SI_SPILL_S64_SAVE killed renamable $sgpr6_sgpr7, %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (store 8 into %stack.1, align 4, addrspace 5)
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# SHARE: renamable $sgpr6_sgpr7 = SI_SPILL_S64_RESTORE %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 8 from %stack.1, align 4, addrspace 5)
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# SHARE: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr6_sgpr7, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit undef $vgpr0
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# SHARE: $sgpr5 = SI_SPILL_S32_RESTORE %stack.2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 4 from %stack.2, addrspace 5)
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# SHARE: $vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
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# SHARE: renamable $sgpr6_sgpr7 = SI_SPILL_S64_RESTORE %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 8 from %stack.1, align 4, addrspace 5)
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# SHARE: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr6_sgpr7, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit $vgpr0
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# SHARE: $sgpr5 = SI_SPILL_S32_RESTORE %stack.2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 4 from %stack.2, addrspace 5)
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# NOSHARE: stack:
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# NOSHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
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# NOSHARE: stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
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# NOSHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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# NOSHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
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# NOSHARE: stack-id: 1, callee-saved-register: '', callee-saved-restored: true,
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# NOSHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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# NOSHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
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# NOSHARE: stack-id: 1, callee-saved-register: '', callee-saved-restored: true,
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# NOSHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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# NOSHARE: - { id: 3, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
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# NOSHARE: stack-id: 1, callee-saved-register: '', callee-saved-restored: true,
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# NOSHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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# NOSHARE: SI_SPILL_S32_SAVE $sgpr5, %stack.2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (store 4 into %stack.2, addrspace 5)
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# NOSHARE: SI_SPILL_V32_SAVE killed $vgpr0, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (store 4 into %stack.0, addrspace 5)
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# NOSHARE: SI_SPILL_S64_SAVE killed renamable $sgpr6_sgpr7, %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (store 8 into %stack.1, align 4, addrspace 5)
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# NOSHARE: renamable $sgpr6_sgpr7 = SI_SPILL_S64_RESTORE %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 8 from %stack.1, align 4, addrspace 5)
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# NOSHARE: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr6_sgpr7, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit undef $vgpr0
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# NOSHARE: $sgpr5 = SI_SPILL_S32_RESTORE %stack.2, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 4 from %stack.2, addrspace 5)
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# NOSHARE: SI_SPILL_S32_SAVE $sgpr5, %stack.3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (store 4 into %stack.3, addrspace 5)
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# NOSHARE: $vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
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# NOSHARE: renamable $sgpr6_sgpr7 = SI_SPILL_S64_RESTORE %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 8 from %stack.1, align 4, addrspace 5)
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# NOSHARE: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr6_sgpr7, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit $vgpr0
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# NOSHARE: $sgpr5 = SI_SPILL_S32_RESTORE %stack.3, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr5 :: (load 4 from %stack.3, addrspace 5)
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...
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name: sgpr_spill_wrong_stack_id
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tracksRegLiveness: true
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frameInfo:
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adjustsStack: false
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hasCalls: true
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body: |
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bb.0.bb:
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%8:sreg_32_xm0 = COPY $sgpr5
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%4:vreg_64 = IMPLICIT_DEF
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%3:vgpr_32 = FLAT_LOAD_DWORD %4, 0, 0, 0, implicit $exec, implicit $flat_scr
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%5:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @func + 4, target-flags(amdgpu-rel32-hi) @func + 4, implicit-def dead $scc
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ADJCALLSTACKUP 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5
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dead $sgpr30_sgpr31 = SI_CALL %5, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit undef $vgpr0
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$sgpr5 = COPY %8
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%12:sreg_32_xm0 = COPY $sgpr5
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ADJCALLSTACKDOWN 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5
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ADJCALLSTACKUP 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5
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$vgpr0 = COPY %3
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dead $sgpr30_sgpr31 = SI_CALL %5, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit killed $vgpr0
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$sgpr5 = COPY %12
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ADJCALLSTACKDOWN 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5
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...
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