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Codegen failure for vmull with small vectors
Codegen was failing with an assertion because of unexpected vector operands when legalizing the selection DAG for a MUL instruction. The asserting code was legalizing multiplies for vectors of size 128 bits. It uses a custom lowering to try and detect cases where it can use a VMULL instruction instead of a VMOVL + VMUL. The code was looking for input operands to the MUL that had been sign or zero extended. If it found the extended operands it would drop the sign/zero extension and use the original vector size as input to a VMULL instruction. The code assumed that the original input vector was 64 bits so that after dropping the extension it would fit directly into a D register and could be used as an operand of a VMULL instruction. The input code that trigger the failure used a vector of <4 x i8> that was sign extended to <4 x i32>. It was not safe to drop the sign extension in this case because the original vector is only 32 bits wide. The fix is to insert a sign extension for the vector to reach the required 64 bit size. In this particular example, the vector would need to be sign extented to a <4 x i16>. llvm-svn: 169024
This commit is contained in:
Sebastian Pop
parent
bee049d9ed
commit
f372d2334f
@ -4939,16 +4939,76 @@ static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
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return false;
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}
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/// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
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/// load, or BUILD_VECTOR with extended elements, return the unextended value.
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static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
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/// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
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/// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
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/// We insert the required extension here to get the vector to fill a D register.
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static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
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const EVT &OrigTy,
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const EVT &ExtTy,
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unsigned ExtOpcode) {
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// The vector originally had a size of OrigTy. It was then extended to ExtTy.
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// We expect the ExtTy to be 128-bits total. If the OrigTy is less than
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// 64-bits we need to insert a new extension so that it will be 64-bits.
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assert(ExtTy.is128BitVector() && "Unexpected extension size");
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if (OrigTy.getSizeInBits() >= 64)
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return N;
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// Must extend size to at least 64 bits to be used as an operand for VMULL.
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MVT::SimpleValueType OrigSimpleTy = OrigTy.getSimpleVT().SimpleTy;
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EVT NewVT;
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switch (OrigSimpleTy) {
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default: llvm_unreachable("Unexpected Orig Vector Type");
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case MVT::v2i8:
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case MVT::v2i16:
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NewVT = MVT::v2i32;
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break;
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case MVT::v4i8:
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NewVT = MVT::v4i16;
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break;
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}
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return DAG.getNode(ExtOpcode, N->getDebugLoc(), NewVT, N);
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}
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/// SkipLoadExtensionForVMULL - return a load of the original vector size that
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/// does not do any sign/zero extension. If the original vector is less
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/// than 64 bits, an appropriate extension will be added after the load to
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/// reach a total size of 64 bits. We have to add the extension separately
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/// because ARM does not have a sign/zero extending load for vectors.
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static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
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SDValue NonExtendingLoad =
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DAG.getLoad(LD->getMemoryVT(), LD->getDebugLoc(), LD->getChain(),
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LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
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LD->isNonTemporal(), LD->isInvariant(),
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LD->getAlignment());
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unsigned ExtOp = 0;
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switch (LD->getExtensionType()) {
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default: llvm_unreachable("Unexpected LoadExtType");
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case ISD::EXTLOAD:
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case ISD::SEXTLOAD: ExtOp = ISD::SIGN_EXTEND; break;
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case ISD::ZEXTLOAD: ExtOp = ISD::ZERO_EXTEND; break;
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}
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MVT::SimpleValueType MemType = LD->getMemoryVT().getSimpleVT().SimpleTy;
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MVT::SimpleValueType ExtType = LD->getValueType(0).getSimpleVT().SimpleTy;
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return AddRequiredExtensionForVMULL(NonExtendingLoad, DAG,
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MemType, ExtType, ExtOp);
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}
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/// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
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/// extending load, or BUILD_VECTOR with extended elements, return the
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/// unextended value. The unextended vector should be 64 bits so that it can
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/// be used as an operand to a VMULL instruction. If the original vector size
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/// before extension is less than 64 bits we add a an extension to resize
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/// the vector to 64 bits.
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static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
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if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
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return N->getOperand(0);
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return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
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N->getOperand(0)->getValueType(0),
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N->getValueType(0),
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N->getOpcode());
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if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
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return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
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LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
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LD->isNonTemporal(), LD->isInvariant(),
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LD->getAlignment());
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return SkipLoadExtensionForVMULL(LD, DAG);
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// Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
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// have been legalized as a BITCAST from v4i32.
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if (N->getOpcode() == ISD::BITCAST) {
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@ -5003,7 +5063,8 @@ static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
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// Multiplications are only custom-lowered for 128-bit vectors so that
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// VMULL can be detected. Otherwise v2i64 multiplications are not legal.
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EVT VT = Op.getValueType();
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assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
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assert(VT.is128BitVector() && VT.isInteger() &&
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"unexpected type for custom-lowering ISD::MUL");
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SDNode *N0 = Op.getOperand(0).getNode();
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SDNode *N1 = Op.getOperand(1).getNode();
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unsigned NewOpc = 0;
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@ -5046,9 +5107,9 @@ static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
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// Legalize to a VMULL instruction.
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DebugLoc DL = Op.getDebugLoc();
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SDValue Op0;
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SDValue Op1 = SkipExtension(N1, DAG);
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SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
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if (!isMLA) {
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Op0 = SkipExtension(N0, DAG);
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Op0 = SkipExtensionForVMULL(N0, DAG);
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assert(Op0.getValueType().is64BitVector() &&
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Op1.getValueType().is64BitVector() &&
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"unexpected types for extended operands to VMULL");
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@ -5063,8 +5124,8 @@ static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
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// vaddl q0, d4, d5
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// vmovl q1, d6
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// vmul q0, q0, q1
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SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
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SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
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SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
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SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
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EVT Op1VT = Op1.getValueType();
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return DAG.getNode(N0->getOpcode(), DL, VT,
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DAG.getNode(NewOpc, DL, VT,
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150
test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
Normal file
150
test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
Normal file
@ -0,0 +1,150 @@
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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; PR12281
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; Test generataion of code for vmull instruction when multiplying 128-bit
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; vectors that were created by sign-extending smaller vector sizes.
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;
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; The vmull operation requires 64-bit vectors, so we must extend the original
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; vector size to 64 bits for vmull operation.
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; Previously failed with an assertion because the <4 x i8> vector was too small
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; for vmull.
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; Vector x Constant
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; v4i8
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;
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define void @sextload_v4i8_c(<4 x i8>* %v) nounwind {
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;CHECK: sextload_v4i8_c:
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entry:
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%0 = load <4 x i8>* %v, align 8
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%v0 = sext <4 x i8> %0 to <4 x i32>
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;CHECK: vmull
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%v1 = mul <4 x i32> %v0, <i32 3, i32 3, i32 3, i32 3>
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store <4 x i32> %v1, <4 x i32>* undef, align 8
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ret void;
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}
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; v2i8
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;
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define void @sextload_v2i8_c(<2 x i8>* %v) nounwind {
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;CHECK: sextload_v2i8_c:
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entry:
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%0 = load <2 x i8>* %v, align 8
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%v0 = sext <2 x i8> %0 to <2 x i64>
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;CHECK: vmull
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%v1 = mul <2 x i64> %v0, <i64 3, i64 3>
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store <2 x i64> %v1, <2 x i64>* undef, align 8
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ret void;
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}
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; v2i16
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;
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define void @sextload_v2i16_c(<2 x i16>* %v) nounwind {
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;CHECK: sextload_v2i16_c:
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entry:
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%0 = load <2 x i16>* %v, align 8
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%v0 = sext <2 x i16> %0 to <2 x i64>
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;CHECK: vmull
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%v1 = mul <2 x i64> %v0, <i64 3, i64 3>
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store <2 x i64> %v1, <2 x i64>* undef, align 8
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ret void;
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}
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; Vector x Vector
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; v4i8
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;
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define void @sextload_v4i8_v(<4 x i8>* %v, <4 x i8>* %p) nounwind {
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;CHECK: sextload_v4i8_v:
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entry:
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%0 = load <4 x i8>* %v, align 8
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%v0 = sext <4 x i8> %0 to <4 x i32>
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%1 = load <4 x i8>* %p, align 8
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%v2 = sext <4 x i8> %1 to <4 x i32>
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;CHECK: vmull
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%v1 = mul <4 x i32> %v0, %v2
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store <4 x i32> %v1, <4 x i32>* undef, align 8
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ret void;
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}
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; v2i8
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;
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define void @sextload_v2i8_v(<2 x i8>* %v, <2 x i8>* %p) nounwind {
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;CHECK: sextload_v2i8_v:
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entry:
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%0 = load <2 x i8>* %v, align 8
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%v0 = sext <2 x i8> %0 to <2 x i64>
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%1 = load <2 x i8>* %p, align 8
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%v2 = sext <2 x i8> %1 to <2 x i64>
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;CHECK: vmull
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%v1 = mul <2 x i64> %v0, %v2
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store <2 x i64> %v1, <2 x i64>* undef, align 8
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ret void;
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}
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; v2i16
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;
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define void @sextload_v2i16_v(<2 x i16>* %v, <2 x i16>* %p) nounwind {
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;CHECK: sextload_v2i16_v:
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entry:
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%0 = load <2 x i16>* %v, align 8
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%v0 = sext <2 x i16> %0 to <2 x i64>
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%1 = load <2 x i16>* %p, align 8
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%v2 = sext <2 x i16> %1 to <2 x i64>
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;CHECK: vmull
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%v1 = mul <2 x i64> %v0, %v2
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store <2 x i64> %v1, <2 x i64>* undef, align 8
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ret void;
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}
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; Vector(small) x Vector(big)
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; v4i8 x v4i16
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;
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define void @sextload_v4i8_vs(<4 x i8>* %v, <4 x i16>* %p) nounwind {
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;CHECK: sextload_v4i8_vs:
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entry:
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%0 = load <4 x i8>* %v, align 8
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%v0 = sext <4 x i8> %0 to <4 x i32>
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%1 = load <4 x i16>* %p, align 8
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%v2 = sext <4 x i16> %1 to <4 x i32>
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;CHECK: vmull
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%v1 = mul <4 x i32> %v0, %v2
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store <4 x i32> %v1, <4 x i32>* undef, align 8
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ret void;
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}
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; v2i8
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; v2i8 x v2i16
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define void @sextload_v2i8_vs(<2 x i8>* %v, <2 x i16>* %p) nounwind {
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;CHECK: sextload_v2i8_vs:
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entry:
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%0 = load <2 x i8>* %v, align 8
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%v0 = sext <2 x i8> %0 to <2 x i64>
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%1 = load <2 x i16>* %p, align 8
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%v2 = sext <2 x i16> %1 to <2 x i64>
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;CHECK: vmull
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%v1 = mul <2 x i64> %v0, %v2
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store <2 x i64> %v1, <2 x i64>* undef, align 8
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ret void;
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}
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; v2i16
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; v2i16 x v2i32
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define void @sextload_v2i16_vs(<2 x i16>* %v, <2 x i32>* %p) nounwind {
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;CHECK: sextload_v2i16_vs:
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entry:
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%0 = load <2 x i16>* %v, align 8
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%v0 = sext <2 x i16> %0 to <2 x i64>
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%1 = load <2 x i32>* %p, align 8
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%v2 = sext <2 x i32> %1 to <2 x i64>
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;CHECK: vmull
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%v1 = mul <2 x i64> %v0, %v2
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store <2 x i64> %v1, <2 x i64>* undef, align 8
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ret void;
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}
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