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Add back in r109901, which adds a Compare flag to the target instructions. It's
useful after all. llvm-svn: 110531
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@ -198,6 +198,7 @@ class Instruction {
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bit isReturn = 0; // Is this instruction a return instruction?
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bit isBranch = 0; // Is this instruction a branch instruction?
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bit isIndirectBranch = 0; // Is this instruction an indirect branch?
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bit isCompare = 0; // Is this instruction a comparison instruction?
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bit isBarrier = 0; // Can control flow fall through this instruction?
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bit isCall = 0; // Is this instruction a call instruction?
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bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
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@ -105,6 +105,7 @@ namespace TID {
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IndirectBranch,
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Predicable,
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NotDuplicable,
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Compare,
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DelaySlot,
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FoldableAsLoad,
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MayLoad,
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@ -315,7 +316,7 @@ public:
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bool isIndirectBranch() const {
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return Flags & (1 << TID::IndirectBranch);
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}
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/// isConditionalBranch - Return true if this is a branch which may fall
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/// through to the next instruction or may transfer control flow to some other
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/// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
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@ -340,6 +341,11 @@ public:
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return Flags & (1 << TID::Predicable);
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}
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/// isCompare - Return true if this instruction is a comparison.
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bool isCompare() const {
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return Flags & (1 << TID::Compare);
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}
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/// isNotDuplicable - Return true if this instruction cannot be safely
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/// duplicated. For example, if the instruction has a unique labels attached
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/// to it, duplicating it would cause multiple definition errors.
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@ -102,6 +102,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
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isReturn = R->getValueAsBit("isReturn");
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isBranch = R->getValueAsBit("isBranch");
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isIndirectBranch = R->getValueAsBit("isIndirectBranch");
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isCompare = R->getValueAsBit("isCompare");
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isBarrier = R->getValueAsBit("isBarrier");
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isCall = R->getValueAsBit("isCall");
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canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
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@ -123,6 +123,7 @@ namespace llvm {
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bool isReturn;
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bool isBranch;
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bool isIndirectBranch;
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bool isCompare;
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bool isBarrier;
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bool isCall;
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bool canFoldAsLoad;
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@ -270,6 +270,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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if (Inst.isReturn) OS << "|(1<<TID::Return)";
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if (Inst.isBranch) OS << "|(1<<TID::Branch)";
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if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
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if (Inst.isCompare) OS << "|(1<<TID::Compare)";
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if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
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if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
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if (Inst.isCall) OS << "|(1<<TID::Call)";
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