From fb9c4c2edcb68a1f65a936102e8a1dbaf6cc7682 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Tue, 20 Mar 2007 22:32:39 +0000
Subject: [PATCH] Updated.

llvm-svn: 35229
---
 lib/Target/ARM/README.txt | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/lib/Target/ARM/README.txt b/lib/Target/ARM/README.txt
index c155e206334..8af07ccffb6 100644
--- a/lib/Target/ARM/README.txt
+++ b/lib/Target/ARM/README.txt
@@ -470,4 +470,9 @@ More register scavenging work:
 
 //===---------------------------------------------------------------------===//
 
-Teach LSR about ARM addressing modes.
+More LSR enhancements possible:
+
+1. Teach LSR about pre- and post- indexed ops to allow iv increment be merged
+   in a load / store.
+2. Allow iv reuse even when a type conversion is required. For example, i8
+   and i32 load / store addressing modes are identical.