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Author SHA1 Message Date
Nadav Rotem
07b7d6858d Reduce the runtime of the test. Keep only the interesting cases. 
llvm-svn: 133381
 2011-06-19 08:12:43 +00:00
Nick Lewycky
46eba338e9 Revert r133373. I was going to use this to teach the Verifier to verify constant 
expressions, but Chris wants to instead reduce the set of possible constant
expression types.

llvm-svn: 133374
 2011-06-19 03:30:32 +00:00
Nick Lewycky
5e8a997ea7 Add the remaining instructions/constant expressions as Operators so that code 
can manipulate instructions and constantexpr's uniformly. No users yet though.

llvm-svn: 133373
 2011-06-19 02:26:33 +00:00
Chris Lattner
6aa403748e Remove support for parsing the "type i32" syntax for defining a numbered 
top level type without a specified number.  This syntax isn't documented
and blocks forward progress.

llvm-svn: 133371
 2011-06-19 00:03:46 +00:00
Chris Lattner
22af594f89 revert r133368, apparently I missed the tests to be updated. 
llvm-svn: 133369
 2011-06-18 23:51:31 +00:00
Chris Lattner
6ff60dbed1 Remove support for parsing the "type i32" syntax for defining a numbered 
top level type without a specified number.  This asmprinter has never
generated this, as you can tell by no tests being updated.  It also isn't
documented.

llvm-svn: 133368
 2011-06-18 23:38:57 +00:00
Chris Lattner
c247005424 fix the varargs version of StructType::get to not require an LLVMContext, making usage 
much cleaner.

llvm-svn: 133364
 2011-06-18 22:48:56 +00:00
Chris Lattner
b93873f487 eliminate some pointless virtual methods. 
llvm-svn: 133363
 2011-06-18 22:15:47 +00:00
Chris Lattner
d8515bc2d6 simplify some code. 
llvm-svn: 133362
 2011-06-18 21:46:23 +00:00
Chris Lattner
6632283a47 now that Type::getDescription() is dead, the TypePrinting class can move from Assembly/Writer.h to being 
a private class in AsmWriter.cpp.

llvm-svn: 133361
 2011-06-18 21:23:04 +00:00
Chris Lattner
50b274b1cb eliminate the Type::getDescription() method, using "<<" instead. This 
removes some gunk from LLVMContext.

llvm-svn: 133360
 2011-06-18 21:18:23 +00:00
Chris Lattner
db3efb92c5 improve some comments. 
llvm-svn: 133359
 2011-06-18 21:02:49 +00:00
Chris Lattner
04676ebdd4 remove an unreduced testcase. 
llvm-svn: 133356
 2011-06-18 19:12:59 +00:00
Chris Lattner
0fe414c07e rework the remaining autoupgrade logic to use a StringRef instead of creating a 
temporary std::string for every function being checked.

llvm-svn: 133355
 2011-06-18 18:56:39 +00:00
Benjamin Kramer
1525b80eef Directly print to a raw_ostream instead of printing to a buffer first. 
llvm-svn: 133352
 2011-06-18 14:42:47 +00:00
Benjamin Kramer
a16cba3e83 Simplify code. No functionality change. 
llvm-svn: 133351
 2011-06-18 14:42:42 +00:00
Benjamin Kramer
0475214748 Simplify code. No change in functionality. 
llvm-svn: 133350
 2011-06-18 13:53:47 +00:00
Hans Wennborg
6229bbd9c0 MC: Allow .common as alias for .comm assembler directive. PR10116. 
llvm-svn: 133349
 2011-06-18 13:51:54 +00:00
Benjamin Kramer
0b4d4ce7c1 Don't allocate empty read-only SmallVectors during SelectionDAG deallocation. 
llvm-svn: 133348
 2011-06-18 13:13:44 +00:00
Benjamin Kramer
8fa1866146 Remove unused but set variables. 
llvm-svn: 133347
 2011-06-18 11:09:41 +00:00
Hans Wennborg
e1d53b6e2b Fix PR10103: Less code for enum type translation. 
In cases such as the attached test, where the case value for a switch
destination is used in a phi node that follows the destination, it
might be better to replace that value with the condition value of the
switch, so that more blocks can be folded away with
TryToSimplifyUncondBranchFromEmptyBlock because there are less
conflicts in the phi node.

llvm-svn: 133344
 2011-06-18 10:28:47 +00:00
Nick Lewycky
36a76a5c77 Add test for r133251. 
llvm-svn: 133339
 2011-06-18 07:23:25 +00:00
Cameron Zwarich
09c312acad When scalar replacement returns a vector type, only accept it if the vector 
type's bitwidth matches the (allocated) size of the alloca. This severely
pessimizes vector scalar replacement when the only vector type being used is
something like <3 x float> on x86 or ARM whose allocated size matches a
<4 x float>.

I hope to fix some of the flawed assumptions about allocated size throughout
scalar replacement and reenable this in most cases.

llvm-svn: 133338
 2011-06-18 06:17:51 +00:00
Chris Lattner
ad5400fa72 rip out a ton of intrinsic modernization logic from AutoUpgrade.cpp, which is 
for pre-2.9 bitcode files.  We keep x86 unaligned loads, movnt, crc32, and the
target indep prefetch change.

As usual, updating the testsuite is a PITA.

llvm-svn: 133337
 2011-06-18 06:05:24 +00:00
Cameron Zwarich
00255ad84e Fix an invalid bitcast crash that occurs when doing a partial memset of a vector 
alloca. Fixes part of <rdar://problem/9580800>.

llvm-svn: 133336
 2011-06-18 05:47:49 +00:00
Cameron Zwarich
d6e767ca48 Remove a pointless assignment. Nothing checks the value of VectorTy anymore now 
unless ScalarKind is Vector.

llvm-svn: 133335
 2011-06-18 05:47:45 +00:00
Jakob Stoklund Olesen
7aee390412 Use the correct comparator to avoid depending on pointer values. 
This should fix the Linux buildbots.

llvm-svn: 133334
 2011-06-18 05:44:55 +00:00
Jakob Stoklund Olesen
f190283688 Store CodeGenRegisters as pointers so they won't be reallocated. 
Reuse the CodeGenRegBank DenseMap in a few places that would build their
own or use linear search.

llvm-svn: 133333
 2011-06-18 04:26:06 +00:00
Jakob Stoklund Olesen
d446052d33 Remove MethodProtos/MethodBodies and allocation_order_begin/end. 
Targets that need to change the default allocation order should use the
AltOrders mechanism instead. See the X86 and ARM targets for examples.

The allocation_order_begin() and allocation_order_end() methods have been
replaced with getRawAllocationOrder(), and there is further support
functions in RegisterClassInfo.

It is no longer possible to insert arbitrary code into generated
register classes. This is a feature.

llvm-svn: 133332
 2011-06-18 03:08:20 +00:00
Jakob Stoklund Olesen
481c6beee6 Delete unneeded allocation order override. 
llvm-svn: 133331
 2011-06-18 02:30:02 +00:00
Jakob Stoklund Olesen
6346426b8c Switch ARM to using AltOrders instead of MethodBodies. 
This slightly changes the GPR allocation order on Darwin where R9 is not
a callee-saved register:

Before: %R0 %R1 %R2 %R3 %R12 %R9 %LR %R4 %R5 %R6 %R8 %R10 %R11
After:  %R0 %R1 %R2 %R3 %R9 %R12 %LR %R4 %R5 %R6 %R8 %R10 %R11
llvm-svn: 133326
 2011-06-18 01:14:46 +00:00
Jakob Stoklund Olesen
434b0e8aef Switch x86 to using AltOrders instead of MethodBodies. 
llvm-svn: 133325
 2011-06-18 01:14:43 +00:00
Galina Kistanova
36039fd720 Moved to the right place. 
llvm-svn: 133324
 2011-06-18 00:59:37 +00:00
Jakob Stoklund Olesen
5502137e83 Reserve D16-D13 on subtargets that don't support them. 
llvm-svn: 133321
 2011-06-18 00:53:27 +00:00
Jakob Stoklund Olesen
5da811d840 Provide AltOrders for specifying alternative allocation orders. 
A register class can define AltOrders and AltOrderSelect instead of
defining method protos and bodies. The AltOrders lists can be defined
with set operations, and TableGen can verify that the alternative
allocation orders only contain valid registers.

This is currently an opt-in feature, and it is still possible to
override allocation_order_begin/end. That will not be true for long.

llvm-svn: 133320
 2011-06-18 00:50:49 +00:00
Bill Wendling
265a3f9032 * Override the "EmitBytes" function, since it can sneak values in that way. 
* Make this used only if CFI is used.

llvm-svn: 133319
 2011-06-18 00:19:35 +00:00
Eric Christopher
169d53e1e0 Fix UMULO support for 2x register width to allow the full 
range without a libcall to a new mulo<mode> libcall
that we'd have to create.

Finishes the rest of rdar://9090077 and rdar://9210061

llvm-svn: 133318
 2011-06-18 00:09:57 +00:00
Bill Wendling
83d5b74f00 Remove false assertion. 
llvm-svn: 133314
 2011-06-17 23:42:01 +00:00
Jakob Stoklund Olesen
8c156f19ec Only call TRI::getRawAllocationOrder to resolve a target-dependent hint. 
llvm-svn: 133313
 2011-06-17 23:26:52 +00:00
Jakob Stoklund Olesen
fb9f0e74cf Zap the last reference to allocation_order_begin(). 
llvm-svn: 133310
 2011-06-17 23:17:13 +00:00
Jakob Stoklund Olesen
e01d928b0f SI, DI, BP, and SP don't have 8-bit sub-registers in x86 mode. 
llvm-svn: 133308
 2011-06-17 23:15:00 +00:00
Eric Christopher
04c9154cba Fix comment. 
llvm-svn: 133307
 2011-06-17 22:35:59 +00:00
Matt Beaumont-Gay
d43d674bfb Fix -Asserts build 
llvm-svn: 133305
 2011-06-17 22:21:12 +00:00
Chad Rosier
0dc865af56 Revert r133285. Causing odd failures on Dragonegg. 
llvm-svn: 133301
 2011-06-17 22:08:25 +00:00
Bill Wendling
918a35a41b Disable for another investigation. 
llvm-svn: 133299
 2011-06-17 21:44:15 +00:00
Devang Patel
65e272ee15 Set debug loc for new preheader's terminator. 
llvm-svn: 133298
 2011-06-17 21:36:44 +00:00
Bill Wendling
be4fd10d84 Support only DwarfCFI or SjLj exception handling in LSDA decoder. 
llvm-svn: 133297
 2011-06-17 21:31:43 +00:00
Bill Wendling
530eece33e SjLj exception handling LSDA decoding support wasn't represented correctly. Use 
the correct values, etc. In particular, the exception handling type is SjLj, not
ARM.

llvm-svn: 133296
 2011-06-17 21:29:06 +00:00
Bill Wendling
a31de72e6a Disable to investigate ARM failure. 
llvm-svn: 133293
 2011-06-17 21:09:50 +00:00
Bill Wendling
1d4e48661b Use the verbose asm flag instead of a new flag for decoding the LSDA. 
llvm-svn: 133292
 2011-06-17 20:55:01 +00:00