Commit Graph

1197 Commits

Author SHA1 Message Date
Eli Friedman
f6cac8a620 Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
llvm-svn: 135337
2011-07-16 02:41:28 +00:00
Eli Friedman
6bd9cfed88 PR10370: Make sure we know how to relax push correctly on x86-64.
llvm-svn: 135303
2011-07-15 21:28:39 +00:00
Owen Anderson
7a380bac06 Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
llvm-svn: 135290
2011-07-15 18:46:47 +00:00
Jim Grosbach
6122eb0fff ARM diagnostic when 's' suffix on mnemonic that can't set flags.
For example, "mlss r0, r1, r2, r3".

The MLS instruction does not have a flag-setting variant.

llvm-svn: 135203
2011-07-14 22:04:21 +00:00
Jim Grosbach
7656c6f97e Add some testcases for ARM MLA/MLS instructions.
llvm-svn: 135196
2011-07-14 21:43:05 +00:00
Jim Grosbach
2ab898973a ARM MCRR/MCRR2 immediate operand range checking.
llvm-svn: 135192
2011-07-14 21:26:42 +00:00
Jim Grosbach
27ebbba831 ARM MCR/MCR2 assembly parsing operand constraints.
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.

llvm-svn: 135189
2011-07-14 21:19:17 +00:00
Jim Grosbach
09b5985799 Enable some tests we now handle correctly.
llvm-svn: 135185
2011-07-14 21:02:23 +00:00
Jim Grosbach
aebb9cdf68 Update ARM Assembly of LDM/STM.
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.

llvm-svn: 135168
2011-07-14 18:35:38 +00:00
Jim Grosbach
ebbd82a248 ARM ISB assembly parsing tests.
llvm-svn: 135158
2011-07-14 18:02:25 +00:00
Jim Grosbach
9bbc2007df ARM ISB instruction assembly parsing.
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.

llvm-svn: 135156
2011-07-14 18:00:31 +00:00
Jim Grosbach
76bd4e6f75 ARM tests for EOR instruction parsing and encoding.
llvm-svn: 135119
2011-07-14 00:22:21 +00:00
Jim Grosbach
fe9c954c0f Remove duplicate tests.
llvm-svn: 135117
2011-07-14 00:19:19 +00:00
Jim Grosbach
4b63d59acb ARM Assembler support for DSB instruction.
Add instalias for default 'sy' option. Add tests.

llvm-svn: 135116
2011-07-14 00:18:13 +00:00
Jim Grosbach
5a96cebd81 ARM Assembler support for DMB instruction.
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".

llvm-svn: 135109
2011-07-13 23:40:38 +00:00
Jim Grosbach
c0ec4205e2 ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.

llvm-svn: 135102
2011-07-13 22:59:38 +00:00
Jim Grosbach
25a4b8922d ARM parsing and encoding tests for CMN/CMP.
llvm-svn: 135098
2011-07-13 22:26:58 +00:00
Jim Grosbach
d5e74991f0 Shuffle ARM assembly tests a bit.
llvm-svn: 135095
2011-07-13 22:19:10 +00:00
Jim Grosbach
fd2ebb4552 Range checking for CDP[2] immediates.
llvm-svn: 135092
2011-07-13 22:01:08 +00:00
Jim Grosbach
d3b15141b8 Fix predicates for Thumb co-processor instructions.
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

llvm-svn: 135081
2011-07-13 21:14:23 +00:00
Jim Grosbach
c7e0941dac Testcases for ARM assembly BX/BXJ instructions.
llvm-svn: 135078
2011-07-13 20:25:46 +00:00
Jim Grosbach
0313701671 Testcases for ARM assembly BLX/BL instructions.
llvm-svn: 135072
2011-07-13 20:11:04 +00:00
Jim Grosbach
0caa098513 Range checking for 16-bit immediates in ARM assembly.
llvm-svn: 135071
2011-07-13 20:10:10 +00:00
Jim Grosbach
9e021b5281 Add tests for ARM parsing of 'BKPT' instruction.
llvm-svn: 135063
2011-07-13 19:17:36 +00:00
Jim Grosbach
ce9b6636b3 Fix copy-pasto.
llvm-svn: 135062
2011-07-13 19:16:30 +00:00
Jim Grosbach
9d1a4de9e6 Add tests for ARM parsing of 'BIC' instruction.
llvm-svn: 135061
2011-07-13 19:12:32 +00:00
Jim Grosbach
7aea4b177f Add some FIXMEs.
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.

llvm-svn: 135060
2011-07-13 19:10:23 +00:00
Jim Grosbach
9b9604762e Add tests for ARM parsing of 'AND' instruction.
llvm-svn: 135056
2011-07-13 18:55:14 +00:00
Jim Grosbach
5c366bfb36 Improve ARM assembly parsing diagnostics a bit.
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.

llvm-svn: 135055
2011-07-13 18:49:30 +00:00
Jim Grosbach
a0a947a8ca Add tests for ARM parsing of 'ADD' instruction
llvm-svn: 135053
2011-07-13 18:12:46 +00:00
Jim Grosbach
7dbb39dffa Destination register operand is optional for ADC and SBC ARM.
llvm-svn: 135052
2011-07-13 17:57:17 +00:00
Jim Grosbach
5db1296fcd Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.

llvm-svn: 135049
2011-07-13 17:50:29 +00:00
Jim Grosbach
295e53b228 Add check for predicate w/o S bit.
llvm-svn: 134987
2011-07-12 16:25:04 +00:00
Jim Grosbach
fae61bb435 Fix recognition of ARM 'adcs' mnemonic.
The 'CS' is not a predication suffix in this case.

llvm-svn: 134903
2011-07-11 17:09:57 +00:00
Jim Grosbach
93f2ebb5e7 Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.

llvm-svn: 134902
2011-07-11 16:48:36 +00:00
Evan Cheng
1346a63a0f - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884
2011-07-11 03:57:24 +00:00
Evan Cheng
71dc177796 Add support for ARM / Thumb mode switching with .code 16 and .code 32.
llvm-svn: 134760
2011-07-08 22:36:29 +00:00
Evan Cheng
952943f744 Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
llvm-svn: 134590
2011-07-07 03:55:05 +00:00
Kevin Enderby
43cb64711d Update MC/ELF/relocation.s with change to X86 PUSH64i8 in r134501.
llvm-svn: 134511
2011-07-06 17:55:20 +00:00
Kevin Enderby
59ba10f2ac Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a
push with a small constant produces a 2-byte push.

llvm-svn: 134501
2011-07-06 17:23:46 +00:00
Eli Friedman
9765ae0015 Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.
llvm-svn: 134424
2011-07-05 18:21:20 +00:00
Joerg Sonnenberger
708b6e085d Recognize the xstorerng alias for VIA PadLock's xstore instruction.
llvm-svn: 134126
2011-06-30 01:38:03 +00:00
Jim Grosbach
88387d64d6 Asm parser range checking on .<size> <value> directives.
For example, ".byte 256" would previously assert() when emitting an object
file. Now it generates a diagnostic that the literal value is out of range.

rdar://9686950

llvm-svn: 134069
2011-06-29 16:05:14 +00:00
Jim Grosbach
33470a73f0 ARM Thumb2 asm syntax optional destination operand for binary operators.
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
and r1, #ff
and r1, r1, #ff

rdar://9672867

llvm-svn: 133973
2011-06-28 00:19:13 +00:00
Jim Grosbach
190b9d7ec0 ARM Assembly support for Thumb mov-immediate.
Correctly parse the forms of the Thumb mov-immediate instruction:
  1. 8-bit immediate 0-255.
  2. 12-bit shifted-immediate.

The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.

llvm-svn: 133966
2011-06-27 23:54:06 +00:00
Jim Grosbach
7c950cf36c ARM assembler support for ldmfd/stmfd mnemonics.
llvm-svn: 133936
2011-06-27 20:32:18 +00:00
Jim Grosbach
7157b0228f ARM assembler support for vpush/vpop.
Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.

rdar://9683231

llvm-svn: 133932
2011-06-27 20:00:07 +00:00
Jim Grosbach
210c7054ac ARM Assembly syntax support for arithmetic implied dest operand.
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
  sub r2, r2, #6
  sub r2, #6

rdar://9682597

llvm-svn: 133925
2011-06-27 19:09:15 +00:00
Jim Grosbach
f8b05a7bbb Move ARM-specific test to ARM directory.
Hopefully make the x86-target-only Windows bots happy.

llvm-svn: 133856
2011-06-25 01:53:17 +00:00
Jim Grosbach
c10ef9d30c Testcase for r133818
llvm-svn: 133823
2011-06-24 20:59:01 +00:00