Eli Friedman
802029c494
Add support for movntil/movntiq mnemonics. Reported on llvmdev.
...
llvm-svn: 133759
2011-06-23 21:07:47 +00:00
Nick Lewycky
8e5c09b7dc
Add support for assembling "movq" when it's correct to do so, while continuing
...
to emit "movd" across the board to continue supporting a Darwin assembler bug.
This is the reincarnation of r133452.
llvm-svn: 133565
2011-06-21 22:45:41 +00:00
Bob Wilson
5b04895bb8
Revert r133452: "Emit movq for 64-bit register to XMM register moves..."
...
This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.
llvm-svn: 133524
2011-06-21 17:35:13 +00:00
Nick Lewycky
831fb8200d
Emit movq for 64-bit register to XMM register moves, but continue to accept
...
movd when assembling.
llvm-svn: 133452
2011-06-20 18:33:26 +00:00
Hans Wennborg
6229bbd9c0
MC: Allow .common as alias for .comm assembler directive. PR10116.
...
llvm-svn: 133349
2011-06-18 13:51:54 +00:00
Bill Wendling
5ae6b0c972
Improve the heuristic to emit the alias if the number of hard-coded registers
...
are also greater than the alias.
llvm-svn: 133038
2011-06-15 04:31:19 +00:00
Bill Wendling
77d4d62693
Heuristic: If the number of operands in the alias are more than the number of
...
operands in the aliasee, don't print the alias.
llvm-svn: 132963
2011-06-14 03:17:20 +00:00
Roman Divacky
478976c99b
Test that ".byte 1, 2, 3, 4" does the right thing.
...
Requested by nbjoerg!
llvm-svn: 132716
2011-06-07 17:32:17 +00:00
Rafael Espindola
f500121fcf
Basic support for macros with explicit arguments.
...
We still don't handle
* default values
* :req
* :vararg
* \()
llvm-svn: 132656
2011-06-05 02:43:45 +00:00
Nick Lewycky
36e7570fb3
Add support for @GOTPTOFF in i386 mode.
...
llvm-svn: 132643
2011-06-04 17:38:07 +00:00
Bruno Cardoso Lopes
0bdb365634
Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
...
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.
llvm-svn: 132324
2011-05-31 03:33:27 +00:00
Rafael Espindola
9550e237a8
Use %rbp on a 64 bit test.
...
llvm-svn: 132279
2011-05-29 04:04:50 +00:00
Benjamin Kramer
ad67c34014
Move ARM specific test into the ARM subdir.
...
llvm-svn: 132255
2011-05-28 11:01:30 +00:00
Bruno Cardoso Lopes
93eae0fd19
ARM asm parser wasn't able to parse a "mov" instruction while in Thumb
...
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.
llvm-svn: 132233
2011-05-27 23:46:09 +00:00
Charles Davis
cb20ea9935
Add the suffix to the Win64 EH data sections' names if given. Add a test for
...
this. XFAIL'd, because the COFF AsmParser can't handle .section yet.
llvm-svn: 132220
2011-05-27 21:38:47 +00:00
Charles Davis
01cde4d080
Assorted fixes for Win64 EH unwind info emission:
...
- Flip order of bitfields. This gets our output matching GAS.
- Handle case where the end of the prolog wasn't specified.
- If the resulting unwind info struct is less than 8 bytes, pad to 8 bytes.
Add a test for the latter two.
llvm-svn: 132188
2011-05-27 15:10:25 +00:00
Charles Davis
028e424cf3
Add a test for Win64 EH unwind information emission.
...
llvm-svn: 132180
2011-05-27 03:54:43 +00:00
Charles Davis
cf332d9ff7
Add a test for the chained directives that I forgot last time.
...
llvm-svn: 132110
2011-05-26 05:17:43 +00:00
Charles Davis
0021487a8e
Test .seh_startchained and .seh_endchained parsing.
...
Rework how the MCWin64EHUnwindInfo instances are stored. Fix issues with
chained unwind areas exposed by the test that were related to this.
The ChainedParent field had the wrong address, because when the chained unwind
info was added, the addresses shifted around. Now we store the pointers to the
structures, which are now allocated from the MC heap.
llvm-svn: 132106
2011-05-26 02:45:47 +00:00
Charles Davis
ede0f07dae
Add tests for .seh_setframe and .seh_handlerdata parsing. Fix issues with
...
them.
I had to add a special SwitchSectionNoChange method to MCStreamer just for
.seh_handlerdata. If this isn't OK, please let me know, and I'll find some
other way to fix .seh_handlerdata streaming.
llvm-svn: 132084
2011-05-25 21:43:45 +00:00
Charles Davis
6b67ee5130
Add tests for .seh_savereg and .seh_savexmm parsing. Once again, fix the
...
buggy methods that parse these directives.
llvm-svn: 132045
2011-05-25 04:51:25 +00:00
Charles Davis
14a32a9608
Add a test for .seh_pushframe parsing. Fix the bug exposed by it (and another
...
one I found by inspection).
llvm-svn: 132037
2011-05-25 04:08:15 +00:00
Charles Davis
967ee6a30b
Add a test for the .seh_handler directive. Fix problems with the parsing
...
method exposed by the test. While we're at it, simplify the .seh_proc
parsing method.
llvm-svn: 132028
2011-05-25 01:33:42 +00:00
Bruno Cardoso Lopes
3a4aae57f4
Fix PR9762
...
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction
llvm-svn: 132026
2011-05-25 00:35:03 +00:00
Charles Davis
d943eb05ed
Test basic SEH directive-parsing functionality. Fix a latent bug exposed by
...
this test.
llvm-svn: 132004
2011-05-24 21:22:53 +00:00
Chris Lattner
859ce35115
add test from PR9164
...
llvm-svn: 131876
2011-05-22 22:35:34 +00:00
Chris Lattner
009caa6b41
testcase for PR9378
...
llvm-svn: 131875
2011-05-22 22:32:53 +00:00
Johnny Chen
6e8aeaa2f4
Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx
...
Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and
modified ARMDisassemblerCore.cpp a little bit.
llvm-svn: 131859
2011-05-22 17:51:04 +00:00
Rafael Espindola
f114810ec8
adds some attributes to attribute section when cpu is "xscale"
...
(this is what used in Android NDK, when architecture is ARMv5)
patch by Koan-Sin Tan
llvm-svn: 131751
2011-05-20 20:10:34 +00:00
Rafael Espindola
27dbdbdf4c
fixes target address tBL and tBLX and sets relocation type
...
of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)
Patch by koan-sin tan.
llvm-svn: 131748
2011-05-20 20:01:01 +00:00
Jason W Kim
93cb3f967d
This fixes one divergence between LLVM and binutils for ARM in the
...
text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
llvm-svn: 131674
2011-05-19 20:55:25 +00:00
Rafael Espindola
826d41a144
ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S.
...
Fixes PR9934.
We really need to start tblgening the relocation info :-(
llvm-svn: 131669
2011-05-19 20:32:34 +00:00
Johnny Chen
3d6c5f4876
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
...
llvm-svn: 131565
2011-05-18 20:32:41 +00:00
Rafael Espindola
e0b15205c1
sets bit 0 of the function address of thumb function in .symtab
...
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)
Patch by Koan-Sin Tan!
llvm-svn: 131406
2011-05-16 16:17:21 +00:00
Owen Anderson
50766bc2f2
Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.
...
llvm-svn: 131189
2011-05-11 17:00:48 +00:00
Rafael Espindola
e8890f4b16
On MachO, unlike ELF, there should be no relocation to produce the CIE pointer.
...
llvm-svn: 131149
2011-05-10 20:59:42 +00:00
Rafael Espindola
ff4443c82c
In a debug_frame the cfi offset is to the start of the debug_frame section!
...
llvm-svn: 131129
2011-05-10 15:20:23 +00:00
Rafael Espindola
b7c942431f
Add support for producing .deubg_frame sections.
...
llvm-svn: 131121
2011-05-10 03:54:12 +00:00
Jakob Stoklund Olesen
8a075ce7ea
Explicitly request -join-physregs for some tests that depend on it.
...
llvm-svn: 130855
2011-05-04 19:01:59 +00:00
Eric Christopher
4f90f378ee
Remove some random comments that snuck in from somewhere.
...
llvm-svn: 130812
2011-05-04 00:48:02 +00:00
Eric Christopher
1de0dfaab0
xmm0 is an implicit parameter in this and so shouldn't be in the
...
string template.
Fixes rdar://8493866
llvm-svn: 130747
2011-05-03 01:28:32 +00:00
Daniel Dunbar
9a87852114
MCAsmLayout: Add support for computing the symbol offset of variables. Not
...
currently used, because variables don't get reported as being "defined".
llvm-svn: 130524
2011-04-29 18:20:20 +00:00
Daniel Dunbar
1488659798
MC: Change variable symbols to be recognized as defined, by assigning their sections based on FindAssociatedSection().
...
llvm-svn: 130523
2011-04-29 18:20:17 +00:00
Johnny Chen
ac8aeb22e4
Add tests for A8.6.110 NOP.
...
llvm-svn: 130345
2011-04-27 23:29:21 +00:00
Chandler Carruth
74094b8d4a
Remove some hard coded CR-LFs. Some of these were the entire files, one of
...
these was just one line of a file. Explicitly set the eol-style property on the
files to try and ensure this fix stays.
llvm-svn: 130125
2011-04-25 07:11:23 +00:00
Johnny Chen
dfac31bc1b
Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
...
print out ldr, not ldr.n.
rdar://problem/9267772
llvm-svn: 130008
2011-04-22 19:12:43 +00:00
Rafael Espindola
e206800036
Fix relative relocations. This is sufficient for running the rust testsuite with
...
MC :-)
llvm-svn: 129923
2011-04-21 18:36:50 +00:00
Rafael Espindola
032ab8c114
Behave like gnu as when a relocation crosses sections.
...
llvm-svn: 129850
2011-04-20 14:01:45 +00:00
Johnny Chen
d7a6b974bc
Thumb2 BFC was insufficiently encoded.
...
rdar://problem/9292717
llvm-svn: 129619
2011-04-15 22:52:15 +00:00
Johnny Chen
2a183b813d
A8.6.315 VLD3 (single 3-element structure to all lanes)
...
The a bit must be encoded as 0.
rdar://problem/9292625
llvm-svn: 129618
2011-04-15 22:49:08 +00:00
Joerg Sonnenberger
42c3063de0
Add encoding tests for flds/filds
...
llvm-svn: 129589
2011-04-15 19:25:31 +00:00
Chris Lattner
0304b82f80
Fix a ton of comment typos found by codespell. Patch by
...
Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
Johnny Chen
197d67a987
The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
...
(single element or n-element structure to all lanes).
llvm-svn: 129550
2011-04-15 00:10:45 +00:00
Johnny Chen
d58c6d4730
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
...
llvm-svn: 129531
2011-04-14 19:13:28 +00:00
Bill Wendling
0b9c16295a
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias
...
(movzx/movsx) because they give more information. Revert that part of the patch.
llvm-svn: 129498
2011-04-14 01:46:37 +00:00
Bill Wendling
d49591cf21
Have the X86 back-end emit the alias instead of what's being aliased. In most
...
cases, it's much nicer and more informative reading the alias.
llvm-svn: 129497
2011-04-14 01:11:51 +00:00
Johnny Chen
1362fdf7a6
Thumb disassembler did not handle tBRIND (indirect branch) properly.
...
rdar://problem/9280370
llvm-svn: 129480
2011-04-13 21:59:01 +00:00
Johnny Chen
d4a0b55be5
Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).
...
rdar://problem/9280470
llvm-svn: 129471
2011-04-13 21:35:49 +00:00
Johnny Chen
dd6fc153b1
The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.
...
rdar://problem/9279440
llvm-svn: 129469
2011-04-13 21:04:32 +00:00
Johnny Chen
b293311a34
Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.
...
rdar://problem/9276651
llvm-svn: 129462
2011-04-13 19:46:05 +00:00
Johnny Chen
e94b35dc41
Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled.
...
rdar://problem/9276427
llvm-svn: 129456
2011-04-13 17:51:02 +00:00
Johnny Chen
5ae9980472
Add sanity check for Ld/St Dual forms of Thumb2 instructions.
...
rdar://problem/9273947
llvm-svn: 129411
2011-04-12 23:31:00 +00:00
Johnny Chen
e3c070e904
The Thumb2 RFE instructions need to have their second halfword fully specified.
...
In addition, the base register is not rGPR, but GPR with th exception that:
if n == 15 then UNPREDICTABLE
rdar://problem/9273836
llvm-svn: 129391
2011-04-12 21:41:51 +00:00
Johnny Chen
4450794a69
Add bad register checks for Thumb2 Ld/St instructions.
...
rdar://problem/9269047
llvm-svn: 129387
2011-04-12 21:17:51 +00:00
Johnny Chen
4435fc93c9
The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23}
...
be specified as '1' (add = TRUE).
Also add a utility function for Thumb2.
llvm-svn: 129377
2011-04-12 18:48:00 +00:00
Johnny Chen
aaaa46cee2
Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple.
...
llvm-svn: 129365
2011-04-12 17:09:04 +00:00
Rafael Espindola
5c5bb3e9a6
Fix the case of a .cfi_rel_offset before any .cfi_def_cfa_offset.
...
llvm-svn: 129362
2011-04-12 16:12:03 +00:00
Rafael Espindola
7c4de15c7b
Implement .cfi_same_value.
...
llvm-svn: 129361
2011-04-12 15:31:05 +00:00
Johnny Chen
156517d4d2
Add one test case (svc).
...
llvm-svn: 129327
2011-04-12 00:21:48 +00:00
Eric Christopher
b01713088d
Match case for invalid constant error messages and add a new
...
test for invalid hexadecimals.
llvm-svn: 129326
2011-04-12 00:18:03 +00:00
Johnny Chen
58713f0ec2
A8.6.16 B
...
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;
rdar://problem/9268681
llvm-svn: 129325
2011-04-12 00:14:49 +00:00
Eric Christopher
2dc03456d0
Test for invalid constant expr addition - bad octal constant.
...
llvm-svn: 129323
2011-04-12 00:03:38 +00:00
Johnny Chen
443a6902bf
Thumb disassembler was erroneously rejecting "blx sp" instruction.
...
rdar://problem/9267838
llvm-svn: 129320
2011-04-11 23:33:30 +00:00
Rafael Espindola
a1fb8a36f9
Implement cfi_rel_offset
...
llvm-svn: 129306
2011-04-11 21:49:50 +00:00
Rafael Espindola
873ddd983f
Add test for previous commit.
...
llvm-svn: 129304
2011-04-11 21:41:34 +00:00
Johnny Chen
77f484c5df
Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled.
...
rdar://problem/9266265
llvm-svn: 129298
2011-04-11 21:14:35 +00:00
Johnny Chen
b07cb8fee1
Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as
...
invalid instructions.
llvm-svn: 129286
2011-04-11 18:34:12 +00:00
Chris Lattner
b9b420d588
fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately,
...
InstAlias doesn't allow matching immediate operands, so we have to write
C++ code to do this.
llvm-svn: 129223
2011-04-09 19:41:05 +00:00
Benjamin Kramer
6f39531981
Don't store Twine temporaries, it's not safe.
...
And don't append the name over and over again in the loop.
llvm-svn: 129210
2011-04-09 11:26:27 +00:00
Johnny Chen
e2464aa24a
Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.
...
PR9650
rdar://problem/9257565
llvm-svn: 129147
2011-04-08 19:41:22 +00:00
Johnny Chen
5b7854afa5
Sanity check the option operand for DMB/DSB.
...
PR9648
rdar://problem/9257634
llvm-svn: 129146
2011-04-08 19:18:07 +00:00
Johnny Chen
2bb229ed27
MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it.
...
Add tests for that.
llvm-svn: 129137
2011-04-08 17:29:58 +00:00
Johnny Chen
16ed2c18a0
Add sanity checking for bad register specifier(s) for the DPFrm instructions.
...
Add more test cases to exercise the logical branches related to the above change.
llvm-svn: 129117
2011-04-08 00:29:09 +00:00
Rafael Espindola
c2955605da
Update tests
...
llvm-svn: 129116
2011-04-07 23:51:25 +00:00
Johnny Chen
0b8e3b20f7
Add a VEXT test.
...
llvm-svn: 129111
2011-04-07 22:04:01 +00:00
Rafael Espindola
a27969f537
Add support for .skip.
...
Patch by Roman Divacky.
Fixes PR9361.
llvm-svn: 129106
2011-04-07 20:26:23 +00:00
Johnny Chen
5d23dd2116
Add sanity checking for invalid register encodings for signed/unsigned extend instructions.
...
Add some test cases.
llvm-svn: 129098
2011-04-07 19:28:58 +00:00
Johnny Chen
7198a60b9a
Add sanity checking for invalid register encodings for saturating instructions.
...
llvm-svn: 129096
2011-04-07 19:02:08 +00:00
Johnny Chen
ecc113f223
Add some more comments about checkings of invalid register numbers.
...
And two test cases.
llvm-svn: 129090
2011-04-07 18:33:19 +00:00
Johnny Chen
4c81015af7
Sanity check MSRi for invalid mask values and reject it as invalid.
...
rdar://problem/9246844
llvm-svn: 129050
2011-04-07 01:37:34 +00:00
Johnny Chen
1f028bb23e
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
...
for USAD8 and USADA8.
rdar://problem/9247060
llvm-svn: 129047
2011-04-07 01:05:52 +00:00
Johnny Chen
523f8f38f7
Should also check SMLAD for invalid register values.
...
rdar://problem/9246650
llvm-svn: 129042
2011-04-07 00:50:25 +00:00
Johnny Chen
81aa7d84be
A8.6.393
...
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.
So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
vst2.32 {d0, d2}, [r3, :256], r3
we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^
llvm-svn: 129033
2011-04-06 22:14:48 +00:00
Johnny Chen
96fd9620c8
A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"
...
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.
rdar://problem/9239922
rdar://problem/9239596
llvm-svn: 129027
2011-04-06 20:49:02 +00:00
Johnny Chen
b3130a03a7
Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
...
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.
rdar://problem/9240648
llvm-svn: 129015
2011-04-06 18:27:46 +00:00
Johnny Chen
765dec3867
Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.
...
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid.
rdar://problem/9239347
rdar://problem/9239467
llvm-svn: 128977
2011-04-06 01:18:32 +00:00
Johnny Chen
48b39632aa
Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
...
encodings for DisassembleArithMiscFrm().
rdar://problem/9238659
llvm-svn: 128958
2011-04-05 23:28:00 +00:00
Johnny Chen
359b9a2331
A7.3 register encoding
...
Qd -> bit[12] == 0
Qn -> bit[16] == 0
Qm -> bit[0] == 0
If one of these bits is 1, the instruction is UNDEFINED.
rdar://problem/9238399
rdar://problem/9238445
llvm-svn: 128949
2011-04-05 22:57:07 +00:00
Johnny Chen
cf11408b65
ARM disassembler was erroneously accepting an invalid RSC instruction.
...
Added checks for regs which should not be 15.
rdar://problem/9237734
llvm-svn: 128945
2011-04-05 22:18:07 +00:00
Johnny Chen
6e1367d5dd
ARM disassembler was erroneously accepting an invalid LSL instruction.
...
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.
rdar://problem/9237693
llvm-svn: 128941
2011-04-05 21:49:44 +00:00