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Author SHA1 Message Date
Johnny Chen
f6655e82b3 The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the 
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function.  Add a test case.

llvm-svn: 128226
 2011-03-24 18:40:38 +00:00
Johnny Chen
154393018f Add comments to the handling of opcode CPS3p to reject invalid instruction encoding, 
a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.

llvm-svn: 128220
 2011-03-24 17:04:22 +00:00
Andrew Trick
a50ee2e148 revert r128199 until it can be made to work with Frontend/dependency-gen.c. 
llvm-svn: 128218
 2011-03-24 16:43:37 +00:00
Cameron Zwarich
1991677a8e Debug intrinsics must be skipped at the beginning and ends of blocks, lest they 
affect the generated code.

llvm-svn: 128217
 2011-03-24 16:34:59 +00:00
Jay Foad
008631e572 Fix typo in comment. 
llvm-svn: 128216
 2011-03-24 16:18:19 +00:00
Chris Lattner
3385be615f fix description, PR9542 
llvm-svn: 128214
 2011-03-24 16:13:31 +00:00
Cameron Zwarich
c2a32b3c5c It is enough for the CallInst to have no uses to be made a tail call with a ret 
void; it doesn't need to have a void type.

llvm-svn: 128212
 2011-03-24 15:54:11 +00:00
Devang Patel
f432e2c2df s/UpdateDT/ModifiedDT/g 
llvm-svn: 128211
 2011-03-24 15:35:25 +00:00
NAKAMURA Takumi
cabdaca3c7 Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets. 
FIXME: Some cleanups would be needed.
llvm-svn: 128206
 2011-03-24 07:07:00 +00:00
NAKAMURA Takumi
cb3235ade0 llvm-stub.cpp: mingw-w64 tweak. 
llvm-svn: 128205
 2011-03-24 07:06:45 +00:00
Evan Cheng
9d660cc8b7 Add comment to clarify what MachineConstantPoolEntry::isMachineConstantPoolEntry() means. 
llvm-svn: 128204
 2011-03-24 06:28:45 +00:00
Evan Cheng
1502266aba Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntry 
entries being compared may not be ARMConstantPoolValue. Without checking
whether they are ARMConstantPoolValue first, and if the stars and moons
are aligned properly, the equality test may return true (when the first few
words of two Constants' values happen to be identical) and very bad things can
happen.

rdar://9125354

llvm-svn: 128203
 2011-03-24 06:20:03 +00:00
Michael J. Spencer
3314c920a5 Remove all uses of PATH_MAX and MAXPATHLEN from PathV2. 
llvm-svn: 128199
 2011-03-24 05:23:40 +00:00
Cameron Zwarich
4d1c5fe9ae Do early taildup of ret in CodeGenPrepare for potential tail calls that have a 
void return type. This fixes PR9487.

llvm-svn: 128197
 2011-03-24 04:52:10 +00:00
Cameron Zwarich
6c983bf746 Use an early return instead of a long if block. 
llvm-svn: 128196
 2011-03-24 04:52:07 +00:00
Cameron Zwarich
6862665125 When UpdateDT is set, DT is invalid, which could cause problems when trying to 
use it later. I couldn't make a test that hits this with the current code.

llvm-svn: 128195
 2011-03-24 04:52:04 +00:00
Cameron Zwarich
6633f15fad Check for TLI so that -codegenprepare can be used from opt. 
llvm-svn: 128194
 2011-03-24 04:51:51 +00:00
Johnny Chen
e61d22bde8 CPS3p: Let's reject impossible imod values by returning false from the DisassembleMiscFrm() function. 
Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing)

Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

Before:
	cpsUnknown imod operand
UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123!

After:
/Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding
0x93 0x1c 0x2 0xf1
^

llvm-svn: 128192
 2011-03-24 02:24:36 +00:00
Johnny Chen
404fb6c07f Load/Store Multiple: 
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add two test cases.

llvm-svn: 128191
 2011-03-24 01:40:42 +00:00
Johnny Chen
0d55ce3734 STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821). 
We now tag them as IndexModePost.

llvm-svn: 128189
 2011-03-24 01:07:26 +00:00
Johnny Chen
f8507c96f1 The r128103 fix to cope with the removal of addressing modes from the MC instructions 
were incomplete.  The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.

llvm-svn: 128186
 2011-03-24 00:28:38 +00:00
Jim Grosbach
f13cc12ddb Runtime dylib simple ARM 24-bit branch relocation support. 
llvm-svn: 128184
 2011-03-23 23:35:17 +00:00
Devang Patel
2cea16e9bb Enable GlobalMerge on darwin. 
llvm-svn: 128183
 2011-03-23 23:34:19 +00:00
Jim Grosbach
06d4707c37 Fix comments. 
llvm-svn: 128182
 2011-03-23 23:32:48 +00:00
Andrew Trick
80893981d6 Revert r128175. 
I'm backing this out for the second time. It was supposed to be fixed by r128164, but the mingw self-host must be defeating the fix.

llvm-svn: 128181
 2011-03-23 23:11:02 +00:00
Evan Cheng
6e799c3c58 Cmp peephole optimization isn't always safe for signed arithmetics. 
int tries = INT_MAX;    
while (tries > 0) {
      tries--;
}

The check should be:
        subs    r4, #1
        cmp     r4, #0
        bgt     LBB0_1

The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop
canonicalization apparently does in this case). cmp #0 would have cleared
it while not changing the N and Z bits. Since BGT is dependent on the V
bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0.

rdar://9172742

llvm-svn: 128179
 2011-03-23 22:52:04 +00:00
Eli Friedman
76fcfaab12 PR9535: add support for splitting and scalarizing vector ISD::FP_ROUND. 
Also cleaning up some duplicated code while I'm here.

llvm-svn: 128176
 2011-03-23 22:18:48 +00:00
Andrew Trick
a7b48f34b1 Reapply Eli's r127852 now that the pre-RA scheduler can spill EFLAGS. 
(target-specific branchless method for double-width relational comparisons on x86)

llvm-svn: 128175
 2011-03-23 22:16:02 +00:00
Jim Grosbach
ef5b20cd6d Split out relocation resolution into target-specific bits. 
llvm-svn: 128173
 2011-03-23 22:06:06 +00:00
Owen Anderson
f473d3cff9 The high bit of a Thumb2 ADR's offset is stored in bit 26, not bit 25. 
This fixes 464.h264ref with the integrated assembler.

llvm-svn: 128172
 2011-03-23 22:03:44 +00:00
Jim Grosbach
f7d5f8a831 Fix double-free of Module. 
The ExecutionEngine constructor already added the module, so there's no
need to call addModule() directly. Doing so causes a double-free of the
Module at program termination.

llvm-svn: 128171
 2011-03-23 21:35:02 +00:00
Owen Anderson
b201c7dede Fix a bug introduced by my patch yesterday: BL is a 4-byte instructions like BLX, rather than a 2-byte instruction like B. 
llvm-svn: 128169
 2011-03-23 21:19:56 +00:00
Andrew Trick
b702dae9b2 Ensure that def-side physreg copies are scheduled above any other uses 
so the scheduler can't create new interferences on the copies
themselves. Prior to this fix the scheduler could get stuck in a loop
creating copies.
Fixes PR9509.

llvm-svn: 128164
 2011-03-23 20:42:39 +00:00
Andrew Trick
ca42e62048 whitespace 
llvm-svn: 128163
 2011-03-23 20:40:18 +00:00
Jim Grosbach
451293fb55 Start of relocation resolution for the runtime dyld library. 
llvm-svn: 128161
 2011-03-23 19:52:00 +00:00
Jim Grosbach
a64f8bf9d5 Make sure to report any errors from the runtime dyld. 
llvm-svn: 128160
 2011-03-23 19:51:34 +00:00
Jakob Stoklund Olesen
c62f168ec5 Don't coalesce identical DBG_VALUE instructions prematurely. 
Each of these instructions may have a RegsClobberInsn entry that can't be
ignored. Consecutive ranges are coalesced later when DwarfDebug::emitDebugLoc
merges entries.

llvm-svn: 128155
 2011-03-23 18:37:30 +00:00
Oscar Fuentes
69c955a67e Supports building with a list of targets that does not contain 
X86. Fixes PR9533.

llvm-svn: 128154
 2011-03-23 17:42:13 +00:00
Justin Holewinski
8861d34661 PTX: Improve support for 64-bit addressing 
- Fix bug in ADDRrr/ADDRri/ADDRii selection for 64-bit addresses
- Add comparison selection for i64
- Add zext selection for i32 -> i64
- Add shl/shr/sha support for i64

llvm-svn: 128153
 2011-03-23 16:58:51 +00:00
Anders Carlsson
8681fe2359 Revert r128140 for now. 
llvm-svn: 128149
 2011-03-23 15:51:12 +00:00
Cameron Zwarich
9f72ea0a80 Fix PR9464 by correcting some math that just happened to be right in most cases 
that were hit in practice.

llvm-svn: 128146
 2011-03-23 05:25:55 +00:00
Jakob Stoklund Olesen
6570595e4c Notify the delegate before removing dead values from a live interval. 
The register allocator needs to know when the range shrinks.

llvm-svn: 128145
 2011-03-23 04:43:16 +00:00
Jakob Stoklund Olesen
d75298c7cd Allow the allocation of empty live ranges that have uses. 
Empty ranges may represent undef values.

llvm-svn: 128144
 2011-03-23 04:32:51 +00:00
Jakob Stoklund Olesen
660147b1d8 Dump the register map before rewriting. 
llvm-svn: 128143
 2011-03-23 04:32:49 +00:00
Anders Carlsson
556ad25dec A global variable with internal linkage where all uses are in one function and whose address is never taken is a non-escaping local object and can't alias anything else. 
llvm-svn: 128140
 2011-03-23 02:19:48 +00:00
Andrew Trick
d9c599d01c Added block number and name to isel debug output. 
I'm tired of doing this manually for each checkout.
If anyone knows a better way debug isel for non-trivial tests feel
free to revert and let me know how to do it.

llvm-svn: 128132
 2011-03-23 01:38:28 +00:00
Douglas Gregor
d11c0d2ab8 Update the Clang attribute emitter to handle attributes of 'version' 
kind, and fix serialization/deserialization of IdentifierInfo
attributes. These are requires for the new 'availability' attribute.

llvm-svn: 128130
 2011-03-23 01:05:46 +00:00
Johnny Chen
b4284e3f90 For ARM Disassembler, start a newline to dump the opcode and friends for an instruction. 
Change inspired by llvm-bug 9530 submitted by Jyun-Yan You.

llvm-svn: 128122
 2011-03-22 23:49:46 +00:00
Johnny Chen
b9309ecef1 Add disassembly test cases for: 
A8.6.292 VCMPE

llvm-svn: 128120
 2011-03-22 23:08:56 +00:00
Devang Patel
c323201836 Remove the test. 
llvm-svn: 128119
 2011-03-22 23:07:03 +00:00