llvm-mirror/test/Transforms/SLPVectorizer
Matthew Simpson 14b16e7ee1 [SLP] Truncate expressions to minimum required bit width
This change attempts to produce vectorized integer expressions in bit widths
that are narrower than their scalar counterparts. The need for demotion arises
especially on architectures in which the small integer types (e.g., i8 and i16)
are not legal for scalar operations but can still be used in vectors. Like
similar work done within the loop vectorizer, we rely on InstCombine to perform
the actual type-shrinking. We use the DemandedBits analysis and
ComputeNumSignBits from ValueTracking to determine the minimum required bit
width of an expression.

Differential revision: http://reviews.llvm.org/D15815

llvm-svn: 258404
2016-01-21 16:31:55 +00:00
..
AArch64 [SLP] Truncate expressions to minimum required bit width 2016-01-21 16:31:55 +00:00
AMDGPU [SLPVectorizer] Try different vectorization factors for store chains 2015-07-08 23:40:55 +00:00
ARM
X86 Reapply r257105 "[Verifier] Check that debug values have proper size" 2016-01-15 00:46:17 +00:00
XCore