Jim Lin 8b679a00b6 [AVR] Fix incorrect register state for LDRdPtr ... Summary: LDRdPtr expanded from LDWRdPtr shouldn't define its second operand(SrcReg). The second operand is its source register. Add -verify-machineinstrs into command line of testcases can trigger this error. Reviewers: dylanmckay Reviewed By: dylanmckay Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D75437		2020-03-03 17:34:54 +08:00
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ADCWRdRr.mir
ADDWRdRr.mir
ANDIWRdK.mir
ANDWRdRr.mir
ASRWRd.mir
COMWRd.mir
CPCWRdRr.mir
CPWRdRr.mir
EORWRdRr.mir
FRMIDX.mir
INWRdA.mir
LDDWRdPtrQ.mir	[AVR] Fix incorrect source regclass of LDWRdPtr	2019-06-03 02:31:07 +00:00
LDDWRdYQ.mir
LDIWRdK.mir
LDSWRdK.mir
LDWRdPtr-same-src-dst.mir	[AVR] Fix codegen bug in 16-bit loads	2019-01-20 03:41:08 +00:00
LDWRdPtr.mir	[AVR] Fix incorrect register state for LDRdPtr	2020-03-03 17:34:54 +08:00
LDWRdPtrPd.mir
LDWRdPtrPi.mir
LSLWRd.mir	[AVR] Redefine the 'LSL' instruction as an alias of 'ADD'	2018-09-01 12:23:00 +00:00
LSRWRd.mir
ORIWRdK.mir
ORWRdRr.mir
OUTWARr.mir
POPWRd.mir
PUSHWRr.mir
SBCIWRdK.mir
SBCWRdRr.mir
SEXT.mir	[AVR] Redefine the 'LSL' instruction as an alias of 'ADD'	2018-09-01 12:23:00 +00:00
STDWPtrQRr.mir
STSWKRr.mir
STWPtrPdRr.mir
STWPtrPiRr.mir
STWPtrRr.mir
SUBIWRdK.mir
SUBWRdRr.mir
ZEXT.mir	[AVR] Redefine the 'LSL' instruction as an alias of 'ADD'	2018-09-01 12:23:00 +00:00