llvm-mirror/lib/Target/PowerPC/README.txt
Nate Begeman a0c15f3ffd Put int the getReg cast optimization from x86 so that we generate fewer
move instructions for the register allocator to coalesce.

llvm-svn: 17608
2004-11-08 02:25:40 +00:00

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TODO:
* poor switch statement codegen
* load/store to alloca'd array or struct.
* implement not-R0 register GPR class
* implement scheduling info
* implement do-loop pass
* implement do-loop -> bdnz transform
* implement powerpc-64 for darwin
* implement powerpc-64 for aix
* use stfiwx in float->int
* should hint to the branch select pass that it doesn't need to print the
second unconditional branch, so we don't end up with things like:
b .LBBl42__2E_expand_function_8_674 ; loopentry.24
b .LBBl42__2E_expand_function_8_42 ; NewDefault
b .LBBl42__2E_expand_function_8_42 ; NewDefault
Currently failing tests that should pass:
* MultiSource
|- Applications
| `- hbd: miscompilation