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llvm-mirror/test/tools/llvm-exegesis
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Vy Nguyen 0724050861 Reland [llvm-exegesis] Add benchmark latency option on X86 that uses LBR for more precise measurements. 
Starting with Skylake, the LBR contains the precise number of cycles between the two
        consecutive branches.
        Making use of this will hopefully make the measurements more precise than the
        existing methods of using RDTSC.

                Differential Revision: https://reviews.llvm.org/D77422

New change: check for existence of field `cycles` in perf_branch_entry before enabling this mode.
This should prevent compilation errors when building for older kernel whose headers don't support it.
2020-07-27 12:38:05 -04:00
..
AArch64 [llvm-exegesis] Fix function return generation so it doesn't return register 0 2018-10-10 13:03:23 +00:00
Mips [llvm-exegesis][mips] Expand loadImmediate() 2020-01-13 12:32:13 +01:00
X86 Reland [llvm-exegesis] Add benchmark latency option on X86 that uses LBR for more precise measurements. 2020-07-27 12:38:05 -04:00
lit.local.cfg [llvm-exegesis] Add lit tests (v2). 2018-09-25 13:59:35 +00:00