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0ac8aa21f4
This is the second minimal patch keeping Nios2 target buildable. I'm adding subtarget here and other stuff for frame lowering, instruction, register information methods. I do not add any test cases, as still there are missing parts like DAG selector and assembly printing. I plan to include them into the next patch. Patch by Andrei Grischenko <andrei.l.grischenko@intel.com> Differential Revision: https://reviews.llvm.org/D37256 llvm-svn: 313626
40 lines
1.8 KiB
TableGen
40 lines
1.8 KiB
TableGen
//===-- Nios2Schedule.td - Nios2 Scheduling Definitions ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Functional units across Nios2 chips sets. Based on GCC/Nios2 backend files.
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//===----------------------------------------------------------------------===//
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def ALU : FuncUnit;
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def IMULDIV : FuncUnit;
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for Nios2
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//===----------------------------------------------------------------------===//
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def IIAlu : InstrItinClass;
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def IILoad : InstrItinClass;
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def IIStore : InstrItinClass;
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def IIFlush : InstrItinClass;
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def IIIdiv : InstrItinClass;
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def IIBranch : InstrItinClass;
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def IIPseudo : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// Nios2 Generic instruction itineraries.
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//===----------------------------------------------------------------------===//
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//@ http://llvm.org/docs/doxygen/html/structllvm_1_1InstrStage.html
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def Nios2GenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
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InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>,
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InstrItinData<IILoad , [InstrStage<3, [ALU]>]>,
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InstrItinData<IIStore , [InstrStage<1, [ALU]>]>,
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InstrItinData<IIFlush , [InstrStage<1, [ALU]>]>,
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InstrItinData<IIIdiv , [InstrStage<38, [IMULDIV]>]>,
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InstrItinData<IIBranch , [InstrStage<1, [ALU]>]>
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]>;
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