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a1d10f171e
This patch includes all missing functionality needed to provide first compilation of a simple program that just returns from a function. I've added a test case that checks for "ret" instruction printed in assembly output. Patch by Andrei Grischenko (andrei.l.grischenko@intel.com) Differential revision: https://reviews.llvm.org/D39688 llvm-svn: 320035
120 lines
3.8 KiB
C++
120 lines
3.8 KiB
C++
//===-- Nios2TargetMachine.cpp - Define TargetMachine for Nios2 -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Nios2 target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "Nios2TargetMachine.h"
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#include "Nios2.h"
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#include "Nios2TargetObjectFile.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "nios2"
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extern "C" void LLVMInitializeNios2Target() {
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// Register the target.
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RegisterTargetMachine<Nios2TargetMachine> X(getTheNios2Target());
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}
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static std::string computeDataLayout() {
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return "e-p:32:32:32-i8:8:32-i16:16:32-n32";
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}
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static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
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if (!RM.hasValue())
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return Reloc::Static;
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return *RM;
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}
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static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
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Reloc::Model RM, bool JIT) {
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if (CM)
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return *CM;
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return CodeModel::Small;
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}
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Nios2TargetMachine::Nios2TargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT)
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: LLVMTargetMachine(
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T, computeDataLayout(), TT, CPU, FS, Options,
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getEffectiveRelocModel(RM),
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getEffectiveCodeModel(CM, getEffectiveRelocModel(RM), JIT), OL),
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TLOF(make_unique<Nios2TargetObjectFile>()),
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Subtarget(TT, CPU, FS, *this) {
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initAsmInfo();
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}
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Nios2TargetMachine::~Nios2TargetMachine() {}
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const Nios2Subtarget *
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Nios2TargetMachine::getSubtargetImpl(const Function &F) const {
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Attribute CPUAttr = F.getFnAttribute("target-cpu");
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Attribute FSAttr = F.getFnAttribute("target-features");
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std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString().str()
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: TargetCPU;
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std::string FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString().str()
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: TargetFS;
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auto &I = SubtargetMap[CPU + FS];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = llvm::make_unique<Nios2Subtarget>(TargetTriple, CPU, FS, *this);
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}
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return I.get();
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}
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namespace {
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/// Nios2 Code Generator Pass Configuration Options.
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class Nios2PassConfig : public TargetPassConfig {
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public:
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Nios2PassConfig(Nios2TargetMachine &TM, PassManagerBase *PM)
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: TargetPassConfig(TM, *PM) {}
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Nios2TargetMachine &getNios2TargetMachine() const {
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return getTM<Nios2TargetMachine>();
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}
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void addCodeGenPrepare() override;
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bool addInstSelector() override;
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void addIRPasses() override;
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};
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} // namespace
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TargetPassConfig *Nios2TargetMachine::createPassConfig(PassManagerBase &PM) {
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return new Nios2PassConfig(*this, &PM);
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}
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void Nios2PassConfig::addCodeGenPrepare() {
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TargetPassConfig::addCodeGenPrepare();
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}
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void Nios2PassConfig::addIRPasses() { TargetPassConfig::addIRPasses(); }
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// Install an instruction selector pass using
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// the ISelDag to gen Nios2 code.
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bool Nios2PassConfig::addInstSelector() {
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addPass(createNios2ISelDag(getNios2TargetMachine(), getOptLevel()));
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return false;
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}
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