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6e72fd82c156b0ddb9490eb94de7bda9dae6f4e1
llvm-mirror/test/CodeGen/AMDGPU
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History
Carl Ritson c515c8773d [AMDGPU] Fix WQM failure with single block inactive demote 
Instruction test for inactive kill/demote needs to be based on
actual opcode not whether instruction would be lowered to demote.

Reviewed By: piotr

Differential Revision: https://reviews.llvm.org/D101966
2021-05-06 21:02:26 +09:00
..
GlobalISel
[AMDGPU] SIFoldOperands: clean up tryConstantFoldOp
2021-05-06 09:55:22 +01:00
32-bit-local-address-space.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
aa-points-to-constant-memory.ll
AMDGPU: Skip GetUnderlyingObject check in pointsToConstantMemory
2020-05-09 16:00:08 -04:00
acc-ldst.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
accvgpr-copy.mir
[AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks
2021-04-30 14:10:50 +01:00
add3.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
add_i1.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
add_i64.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
add_i128.ll
[AMDGPU] Switch scalarize global loads ON by default
2017-07-04 17:32:00 +00:00
add_shl.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
add-debug.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
add.i16.ll
[AMDGPU][MC] Corrected decoding of 16-bit literals
2020-07-22 17:20:43 +03:00
add.ll
AMDGPU: Select VOP3 form of add
2019-05-08 22:09:57 +00:00
add.v2i16.ll
[AMDGPU][MC] Corrected decoding of 16-bit literals
2020-07-22 17:20:43 +03:00
addrspacecast-captured.ll
AMDGPU: Fix using old address spaces in some tests
2018-12-05 17:34:59 +00:00
addrspacecast-constantexpr.ll
[IR] Make nosync, nofree and willreturn default for intrinsics.
2020-10-20 11:57:19 +02:00
addrspacecast-initializer-unsupported.ll
[AMDGPU] Rename "LDS lowering" pass name.
2021-04-14 20:19:53 +05:30
addrspacecast-initializer.ll
Support addrspacecast initializers with isNoopAddrSpaceCast
2020-07-31 10:42:43 -04:00
addrspacecast.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
adjust-writemask-invalid-copy.ll
[AMDGPU] Added -mcpu to couple more tests. NFC.
2021-02-03 10:20:18 -08:00
adjust-writemask-vectorized.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
agpr-csr.ll
AMDGPU: Add missing runline to test
2021-04-29 20:59:22 -04:00
agpr-register-count.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
agpr-remat.ll
AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32
2020-07-01 18:58:59 -04:00
alignbit-pat.ll
[AMDGPU] Switch scalarize global loads ON by default
2017-07-04 17:32:00 +00:00
alloc-aligned-tuples-gfx90a.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
alloc-aligned-tuples-gfx908.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
alloc-all-regs-reserved-in-class.mir
RegAlloc: Fix assert if all registers in class reserved
2021-01-31 11:10:04 -05:00
alloca.ll
AllocaInst should store Align instead of MaybeAlign.
2020-05-16 14:53:16 -07:00
always-uniform.ll
DivergencyAnalysis patch for review
2017-06-15 19:33:10 +00:00
amd.endpgm.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
amdgcn-ieee.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
amdgcn-load-offset-from-reg.ll
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
amdgcn.bitcast.ll
[AMDGPU] Fix crash when dag-combining bitcast
2020-08-13 10:23:13 +08:00
amdgcn.private-memory.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdgpu-alias-analysis.ll
[NewPM][AMDGPU] Make amdgpu-aa work with NewPM
2021-01-04 12:36:27 -08:00
amdgpu-codegenprepare-fdiv.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
amdgpu-codegenprepare-fold-binop-select.ll
Revert "[ConstantFold] Fold more operations to poison"
2021-02-04 00:24:02 +09:00
amdgpu-codegenprepare-i16-to-i32.ll
AMDGPU: Generate test checks
2020-01-20 20:03:45 -05:00
amdgpu-codegenprepare-idiv.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
amdgpu-codegenprepare-mul24.ll
AMDGPU: Introduce a flag to disable mul24 intrinsic formation
2019-08-24 22:14:41 +00:00
amdgpu-function-calls-option.ll
AMDGPU: Enable function calls by default
2019-02-28 00:40:32 +00:00
amdgpu-inline.ll
[AMDGPU] Do not check max-bb for a single block callee
2021-03-01 19:48:50 -08:00
amdgpu-mul24-knownbits.ll
[AMDGPU] simplifyI24 - replace GetDemandedBits with SimplifyMultipleUseDemandedBits
2020-02-20 12:03:08 +00:00
amdgpu-reloc-const.ll
[llvm-readobj] - For SHT_REL relocations, don't display an addend.
2020-12-14 12:03:00 +03:00
amdgpu-shader-calling-convention.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
amdgpu-unroll-threshold.ll
[BasicAA] Rename deprecated -basicaa to -basic-aa
2020-06-26 20:41:37 -07:00
amdgpu.private-memory.ll
[AMDGPU, test] Fix use of undef FileCheck var
2021-04-08 09:42:59 +01:00
amdgpu.work-item-intrinsics.deprecated.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdhsa-trap-num-sgprs.ll
[AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logic
2020-07-30 21:41:13 +05:30
amdpal_scratch_mergedshader.ll
[AMDGPU] Enable LICM in the BE pipeline
2018-06-29 16:26:53 +00:00
amdpal-callable.ll
AMDGPU: Move handling of allocation of fixed ABI inputs
2021-02-03 09:27:59 -05:00
amdpal-cs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-elf.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
amdpal-es.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-gs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-hs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-ls.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-cs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-default.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-denormal.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-dx10-clamp.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-es.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-gs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-hs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-ieee.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-ls.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-ps.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-psenable.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-msgpack-vs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-ps.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-psenable.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal-vs.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
amdpal.ll
[AMDGPU] Emit new pal metadata by default
2020-10-26 10:16:17 +01:00
and_or.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
and-gcn.ll
[AMDGPU] Switch scalarize global loads ON by default
2017-07-04 17:32:00 +00:00
and.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
andorbitset.ll
AMDGPU: Fix verifier error with undef source producing s_bitset*
2020-08-05 14:42:20 -04:00
andorn2.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
andorxorinvimm.ll
[AMDGPU] Shrink scalar AND, OR, XOR instructions
2018-12-07 15:33:21 +00:00
annotate-kernel-features-hsa-call.ll
[AMDGPU] Remove error check for indirect calls and add missing queue-ptr
2021-04-20 00:35:17 +05:30
annotate-kernel-features-hsa.ll
AMDGPU: Add IntrWillReturn to intrinsic definitions
2020-06-18 15:38:10 -04:00
annotate-kernel-features.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
annotate-noclobber.ll
AMDGPU: Annotate amdgpu.noclobber for global loads only
2021-01-05 14:47:19 -08:00
anonymous-gv.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
any_extend_vector_inreg.ll
[AMDGPU] Switch scalarize global loads ON by default
2017-07-04 17:32:00 +00:00
anyext.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
are-loads-from-same-base-ptr.ll
AMDGPU: Fix areLoadsFromSameBasePtr for DS atomics
2019-03-27 15:41:00 +00:00
array-ptr-calc-i32.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
array-ptr-calc-i64.ll
AMDGPU: Implement computeKnownBitsForTargetNode for mbcnt
2017-11-13 22:55:05 +00:00
ashr.v2i16.ll
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
asm-printer-check-vcc.mir
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
at-least-one-def-value-assert.mir
[AMDGPU] Define 16 bit VGPR subregs
2020-03-31 11:49:06 -07:00
atomic_cmp_swap_local.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
atomic_load_add.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_load_local.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
atomic_load_sub.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_optimizations_buffer.ll
[AMDGPU] Remove weird target triples from tests. NFC.
2021-03-19 16:48:32 +00:00
atomic_optimizations_global_pointer.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
atomic_optimizations_local_pointer.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
atomic_optimizations_pixelshader.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
atomic_optimizations_raw_buffer.ll
[AMDGPU] Remove weird target triples from tests. NFC.
2021-03-19 16:48:32 +00:00
atomic_optimizations_struct_buffer.ll
[AMDGPU] Remove weird target triples from tests. NFC.
2021-03-19 16:48:32 +00:00
atomic_store_local.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
atomicrmw-nand.ll
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
attr-amdgpu-flat-work-group-size-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
attr-amdgpu-flat-work-group-size-vgpr-limit.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
attr-amdgpu-flat-work-group-size.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
attr-amdgpu-num-sgpr.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 14:10:03 -08:00
attr-amdgpu-num-vgpr.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
attr-amdgpu-waves-per-eu.ll
AMDGPU: Fix amdgpu-flat-work-group-size/amdgpu-waves-per-eu check
2017-07-16 19:38:47 +00:00
attr-unparseable.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
barrier-elimination.ll
[AMDGPU][GlobalISel] Eliminate barrier if workgroup size is not greater than wavefront size
2020-08-26 13:47:51 +01:00
basic-branch.ll
[AMDGPU] Use lowercase for subtarget feature names in RUN lines
2020-10-13 09:02:09 +01:00
basic-call-return.ll
AMDGPU: Fix register name format in tests
2018-03-27 18:39:42 +00:00
basic-loop.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
bfe_uint.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
bfe-combine.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
bfe-patterns.ll
[AMDGPU] Make bfe patterns divergence-aware
2020-10-05 09:55:10 +01:00
bfi_int.ll
[AMDGPU] Add alignment check for v3 to v4 load type promotion
2020-11-01 12:05:34 +05:30
bfm.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
big_alu.ll
AMDGPU: Remove llvm.AMDGPU.clamp intrinsic
2017-02-21 23:46:04 +00:00
bitcast-constant-to-vector.ll
[MachineScheduler] Reduce reordering due to mem op clustering
2020-01-14 19:19:02 +00:00
bitcast-v4f16-v4i16.ll
AMDGPU: Fix some more incorrect check lines
2020-02-26 14:37:22 +00:00
bitcast-vector-extract.ll
IR: Add immarg attribute
2019-03-12 21:02:54 +00:00
bitreverse-inline-immediates.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
bitreverse.ll
[AMDGPU] Better codegen for i64 bitreverse
2021-02-26 15:51:36 +00:00
br_cc.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
branch-condition-and.ll
[AMDGPU] Keep skip branch for ds instructions
2021-03-05 12:34:09 +01:00
branch-relax-bundle.ll
AMDGPU: Fix not accounting for instruction size in bundles
2017-10-04 22:59:12 +00:00
branch-relax-spill.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
branch-relaxation-debug-info.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
branch-relaxation-gfx10-branch-offset-bug.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
branch-relaxation-inst-size-gfx10.ll
MC: Allow getMaxInstLength to depend on the subtarget
2019-05-22 16:28:41 +00:00
branch-relaxation.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
branch-uniformity.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
break-smem-soft-clauses.mir
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
break-vmem-soft-clauses.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
bswap.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
buffer-intrinsics-mmo-offsets.ll
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
buffer-schedule.ll
[AMDGPU] stop buffer_store being moved illegally
2018-02-20 10:03:38 +00:00
bug-sdag-scheduler-cycle.ll
SelectionDAG: Fix bug in ClusterNeighboringLoads
2020-02-12 09:12:55 +01:00
bug-vopc-commute.ll
AMDGPU: Convert tests away from llvm.SI.load.const
2019-01-17 22:47:26 +00:00
build_vector.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
build-vector-insert-elt-infloop.ll
AMDGPU: Move d16 load matching to preprocess step
2019-03-08 20:58:11 +00:00
build-vector-packed-partial-undef.ll
[AMDGPU] Add ISD::FSHR -> ALIGNBIT support
2020-03-12 20:16:57 +00:00
bundle-latency.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
bypass-div.ll
[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
2020-07-08 19:14:49 +01:00
byval-frame-setup.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
call_fs.ll
…
call-argument-types.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
call-constant.ll
[AMDGPU] Remove error check for indirect calls and add missing queue-ptr
2021-04-20 00:35:17 +05:30
call-constexpr.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
call-encoding.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
call-graph-register-usage.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
call-preserved-registers.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
call-return-types.ll
AMDGPU: Improve <2 x i24> arguments and return value handling
2020-09-16 11:21:56 -04:00
call-skip.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
call-to-kernel-undefined.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
call-to-kernel.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
call-waitcnt.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
call-waw-waitcnt.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
callee-frame-setup.ll
[AMDGPU] Fix saving fp and bp
2021-04-12 11:52:55 +02:00
callee-special-input-sgprs-fixed-abi.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
callee-special-input-sgprs.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
callee-special-input-vgprs-packed.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
callee-special-input-vgprs.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
calling-conventions.ll
AMDGPU: Allow i16 shader arguments
2020-01-27 06:55:32 -08:00
captured-frame-index.ll
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
carryout-selection.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
cayman-loop-bug.ll
…
cc-sgpr-limit.ll
[AMDGPU] Adjust number of SGPRs available in Calling Convention
2019-08-28 15:00:45 +00:00
cc-sgpr-over-limit.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
cc-update.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
cf_end.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
cf-loop-on-constant.ll
[LSR] Fix for pre-indexed generated constant offset
2021-04-15 16:44:42 +01:00
cf-stack-bug.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
cgp-addressing-modes-flat.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
cgp-addressing-modes-gfx908.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
cgp-addressing-modes-gfx1030.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
cgp-addressing-modes.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
cgp-bitfield-extract.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
chain-hi-to-lo.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
clamp-modifier.ll
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed
2021-01-04 14:44:10 -06:00
clamp-omod-special-case.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
clamp.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
cluster_stores.ll
[AMDGPU] Autogenerate checks for a clustering test and add GFX10
2021-05-05 13:18:17 +01:00
cluster-flat-loads-postra.mir
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
cluster-flat-loads.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
cmp_shrink.mir
[AMDGPU] Avoid using s_cmpk when src0 is not register
2020-07-14 09:05:53 +01:00
cndmask-no-def-vcc.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
coalesce-identity-copies-undef-subregs.mir
RegisterCoalescer: Prune undef subranges from copy pairs in loops
2021-02-03 13:42:53 -05:00
coalesce-vgpr-alignment.ll
AMDGPU: Remove special case in shouldCoalesce
2021-02-24 14:49:44 -05:00
coalescer_distribute.ll
AMDGPU: Don't use spir_kernel in a test
2018-07-05 17:01:29 +00:00
coalescer_remat.ll
[AMDGPU] Switch AnnotateUniformValues to MemorySSA
2021-05-05 18:34:41 -07:00
coalescer-extend-pruned-subrange.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
coalescer-identical-values-undef.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
coalescer-removepartial-extend-undef-subrange.mir
[RegisterCoalescer] Pass Undefs to extendToIndices()
2020-09-29 08:14:24 +08:00
coalescer-subranges-another-copymi-not-live.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
coalescer-subranges-another-prune-error.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
coalescer-subranges-prune-kill-copy.mir
Fix register coalescer failure to prune value
2019-05-21 19:32:41 +00:00
coalescer-subreg-join.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
coalescer-subregjoin-fullcopy.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
coalescer-with-subregs-bad-identical.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
coalescing_makes_lanes_undef.mir
[RegisterCoalescer] Fix IMPLICIT_DEF init removal for a register on joining
2020-09-24 17:37:03 +03:00
coalescing-subreg-was-undef-but-became-def.mir
[AMDGPU] Add the test from D49097.
2020-05-20 14:34:51 +01:00
coalescing-with-subregs-in-loop-bug.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
code-object-v3.ll
[test] Make ELF tests less reliant on the lexicographical order of non-local symbols
2021-02-13 01:01:06 -08:00
codegen-prepare-addrmode-sext.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
collapse-endcf2.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
collapse-endcf-broken.mir
AMDGPU: Add additional MIR tests for exec mask optimizations
2019-03-27 16:58:30 +00:00
collapse-endcf.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
collapse-endcf.mir
[AMDGPU] Remove fix up operand from SI_ELSE
2020-10-20 19:15:21 +09:00
combine_vloads.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
combine-add-zext-xor.ll
[AMDGPU] Fix a miscompile with S_ADD/S_SUB
2021-02-17 12:24:58 +01:00
combine-and-sext-bool.ll
[AMDGPU] Combine and x, (sext cc from i1) => select cc, x, 0
2017-06-27 18:25:26 +00:00
combine-cond-add-sub.ll
Revert "AMDGPU: Try to commute sub of boolean ext"
2019-12-13 12:49:06 +00:00
combine-ftrunc.ll
Eliminate ftrunc if source is know to be rounded
2017-10-02 16:57:07 +00:00
comdat.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
commute_modifiers.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
commute-compares.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
commute-shifts.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
commute-vop3.mir
[AMDGPU] Make some VOP3 insts commutable
2021-04-28 13:59:08 -04:00
complex-folding.ll
…
computeKnownBits-scalar-to-vector-crash.ll
[SelectionDAG] Don't pass on DemandedElts when handling SCALAR_TO_VECTOR
2018-12-07 09:18:44 +00:00
computeNumSignBits-mul.ll
[AMDGPU] Update autogenerated checks
2019-12-17 16:48:02 +00:00
concat_vectors.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
constant-address-space-32bit.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
constant-fold-imm-immreg.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
constant-fold-mi-operands.ll
AMDGPU: Explicitly define a triple for some tests
2019-06-17 19:25:57 +00:00
control-flow-fastregalloc.ll
[AMDGPU] Save VGPR of whole wave when spilling
2021-04-12 11:01:38 +02:00
control-flow-optnone.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
convergent-inlineasm.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
copy_phys_vgpr64.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
copy-illegal-type.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
copy-overlap-vgpr-kill.mir
AMDGPU: Don't kill super-register with overlapping copy
2020-10-16 09:34:35 -04:00
copy-to-reg.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
couldnt-join-subrange-3.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
cross-block-use-is-not-abi-copy.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
cse-phi-incoming-val.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
csr-gfx10.ll
[AMDGPU] Use pseudo instructions for readlane/writelane
2020-10-29 16:00:53 +00:00
csr-sgpr-spill-live-ins.mir
AMDGPU: Add spilled CSR SGPRs to entry block live ins
2020-12-22 21:55:59 -05:00
ctlz_zero_undef.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
ctlz.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
ctpop16.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
ctpop64.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
ctpop.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
cttz_zero_undef.ll
[AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logic
2020-07-30 21:41:13 +05:30
cube.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
cvt_f32_ubyte.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
cvt_flr_i32_f32.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
cvt_rpi_i32_f32.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
dag-divergence-atomic.ll
[AMDGPU] Update gfx90a memory model support
2021-04-07 22:17:58 +00:00
dag-divergence.ll
AMDGPU: Fix DAG divergence not reporting flat loads
2018-09-04 18:58:19 +00:00
dagcomb-shuffle-vecextend-non2.ll
[DAGCombine] Fix for shuffle to vector extend for non power 2 vectors
2017-10-10 12:45:45 +00:00
dagcombine-reassociate-bug.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
dagcombine-select.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
dagcombine-setcc-select.ll
[AMDGPU] Automatically generate various tests. NFC
2019-08-23 17:58:49 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
dbg-value-ends-sched-region.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
dce-disjoint-intervals.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
dead_copy.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
dead-lane.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
dead-machine-elim-after-dead-lane.ll
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.
2020-01-14 19:26:15 -05:00
debug_frame.ll
[MCAsmInfo] Support UsesCFIForDebug for targets with no exception handling
2021-05-06 04:53:45 +05:30
debug-value2.ll
AMDGPU: Decompose all values to 32-bit pieces for calling conventions
2019-07-19 13:57:44 +00:00
debug-value-scheduler-crash.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
debug-value.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
debug.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
default-fp-mode.ll
AMDGPU: Add some tests for exotic denormal mode combinations
2020-04-02 17:17:12 -04:00
detect-dead-lanes.mir
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
2019-10-10 07:11:33 +00:00
direct-indirect-call.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
directive-amdgcn-target.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
disable_form_clauses.ll
AMDGPU: Use kill instruction to hint soft clause live ranges
2021-02-26 18:26:40 -05:00
disconnected-predset-break-bug.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
div_i128.ll
AMDGPU: Have a few selection failure tests check both paths
2020-08-24 17:46:31 -04:00
diverge-extra-formal-args.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
diverge-interp-mov-lower.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
diverge-switch-default.ll
[InstCombine] fix operands of shouldChangeType() for casted phi transform
2020-02-04 07:45:48 -05:00
divergence-at-use.ll
[AMDGPU] Add amdgpu_kernel for consistency with other tests
2019-07-29 11:48:17 +00:00
divergent-branch-uniform-condition.ll
[AMDGPU] add generated checks for some LIT tests
2020-03-03 11:47:05 +05:30
divrem24-assume.ll
[AMDGPU] Fix some tests that did not specify -mcpu
2020-02-17 14:02:32 +00:00
dpp64_combine.ll
[AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3
2021-02-22 14:59:40 +03:00
dpp64_combine.mir
AMDGPU: Add even aligned VGPR/AGPR register classes
2021-02-24 14:49:37 -05:00
dpp_combine.ll
[AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3
2021-02-22 14:59:40 +03:00
dpp_combine.mir
[AMDGPU] GCNDPPCombine: don't shrink V_ADD_CO_U32 if carry out is used
2021-04-20 09:17:52 +01:00
drop-mem-operand-move-smrd.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
ds_read2_offset_order.ll
AMDGPU/SILoadStoreOptimizer: Improve merging of out of order offsets
2020-01-24 19:45:56 -08:00
ds_read2_superreg.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 14:16:52 -08:00
ds_read2.ll
[AMDGPU] Only use ds_read/write_b128 for alignment >= 16
2021-04-08 08:12:05 +05:30
ds_read2st64.ll
AMDGPU: Match global saddr addressing mode
2020-08-17 15:28:14 -04:00
ds_write2.ll
[AMDGPU] Only use ds_read/write_b128 for alignment >= 16
2021-04-08 08:12:05 +05:30
ds_write2st64.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
ds-alignment.ll
[AMDGPU] Only use ds_read/write_b128 for alignment >= 16
2021-04-08 08:12:05 +05:30
ds-combine-large-stride.ll
[AMDGPU] Better selection of base offset when merging DS reads/writes
2021-02-11 17:46:09 +00:00
ds-combine-with-dependence.ll
[amdgpu] Enable use of AA during codegen.
2020-10-27 09:46:23 -04:00
ds-negative-offset-addressing-mode-loop.ll
AMDGPU: Increase vcc liveness scan threshold
2019-10-20 17:44:17 +00:00
ds-sub-offset.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
duplicate-attribute-indirect.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
dynamic_stackalloc.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
early-if-convert-cost.ll
[AMDGPU] Support for v3i32/v3f32
2019-03-21 12:01:21 +00:00
early-if-convert.ll
AMDGPU: Fix backwards s_cselect_* operands
2020-05-27 09:26:09 -04:00
early-inline-alias.ll
[AMDGPU] Run always inliner early in opt
2017-03-20 18:06:45 +00:00
early-inline.ll
Reapply "AMDGPU: Force inlining if LDS global address is used"
2018-07-10 14:03:41 +00:00
early-tailduplicator-nophis.mir
TailDuplication: Clear NoPHIs property
2019-12-27 14:06:31 -05:00
early-term.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
elf-header-flags-mach.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
elf-header-flags-sramecc.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
elf-header-flags-xnack.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
elf-header-osabi.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
elf-notes.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
elf.ll
[Object] Change ELFObjectFile<ELFT>::getFileFormatName() to use BFD names
2020-03-16 07:42:04 -07:00
elf.metadata.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
elf.r600.ll
[Object] Change ELFObjectFile<ELFT>::getFileFormatName() to use BFD names
2020-03-16 07:42:04 -07:00
else.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
empty-function.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
enable-no-signed-zeros-fp-math.ll
Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control
2019-07-31 21:57:28 +00:00
endcf-loop-header.ll
AMDGPU: Remove old intrinsic uses
2017-05-17 21:38:21 +00:00
endpgm-dce.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
enqueue-kernel.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
exceed-max-sgprs.ll
AMDGPU: Use correct register names in inline assembly
2017-06-08 19:03:20 +00:00
expand-atomicrmw-syncscope.ll
[AMDGPU] Update gfx90a memory model support
2021-04-07 22:17:58 +00:00
expand-scalar-carry-out-select-user.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
expand-si-indirect.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
extend-bit-ops-i16.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
extload-align.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
extload-private.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
extload.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
extra-sroa-after-unroll.ll
[NFC][AMDGPU] Clean up some lit test prefixes
2020-11-11 17:12:37 +00:00
extract_subvector_vec4_vec3.ll
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
extract_vector_dynelt.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
extract_vector_elt-f16.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
extract_vector_elt-f64.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
extract_vector_elt-i8.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
extract_vector_elt-i16.ll
[AMDGPU] Remove cpol, tfe, and swz from MUBUF patterns
2021-03-18 14:36:04 -07:00
extract_vector_elt-i64.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
extract-load-i1.ll
[DAGCombine] Fix bug in load scalarization
2020-11-04 19:02:40 +00:00
extract-lowbits.ll
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
extract-subvector-equal-length.ll
AMDGPU: Remove optnone from a test
2019-10-19 01:34:59 +00:00
extract-subvector.ll
[AMDGPU] Fixed selection error for 64 bit extract_subvector
2020-05-18 14:17:59 -07:00
extract-vector-elt-build-vector-combine.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
extractelt-to-trunc.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
fabs.f16.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
fabs.f64.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fabs.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
fadd64.ll
[AMDGPU] Fix dubious regexes with unescaped brackets. NFC.
2021-04-06 13:17:41 +01:00
fadd-fma-fmul-combine.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
fadd.f16.ll
[AMDGPU] Precommit some scheduler related test updates
2020-02-28 11:20:58 +00:00
fadd.ll
Utilize new SDNode flag functionality to expand current support for fadd
2018-06-18 23:44:59 +00:00
fail-select-buffer-atomic-fadd.ll
[AMDGPU] Unify intrinsic ret/nortn interface
2020-09-15 15:26:42 -07:00
fast-ra-kills-vcc.mir
[AMDGPU] Remove scratch rsrc from spill pseudos
2020-11-12 15:23:37 -08:00
fast-regalloc-bundles.mir
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fast-unaligned-load-store.global.ll
[AMDGPU] Make some VOP3 insts commutable
2021-04-28 13:59:08 -04:00
fast-unaligned-load-store.private.ll
[AMDGPU] Make some VOP3 insts commutable
2021-04-28 13:59:08 -04:00
fastregalloc-illegal-subreg-physreg.mir
Reapply "RegAllocFast: Rewrite and improve"
2020-09-30 10:35:25 -04:00
fastregalloc-self-loop-heuristic.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
fcanonicalize-elimination.ll
AMDGPU: Match global saddr addressing mode
2020-08-17 15:28:14 -04:00
fcanonicalize.f16.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
fcanonicalize.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
fceil64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
fceil.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
fcmp64.ll
[AMDGPU] Fix dubious regexes with unescaped brackets. NFC.
2021-04-06 13:17:41 +01:00
fcmp-cnd.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
fcmp-cnde-int-args.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
fcmp.f16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
fcmp.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
fconst64.ll
[AMDGPU] Switch scalarize global loads ON by default
2017-07-04 17:32:00 +00:00
fcopysign.f16.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fcopysign.f32.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fcopysign.f64.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fdiv32-to-rcp-folding.ll
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed
2021-01-04 14:44:10 -06:00
fdiv-nofpexcept.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
fdiv.f16.ll
AMDGPU: Match global saddr addressing mode
2020-08-17 15:28:14 -04:00
fdiv.f64.ll
AMDGPU: Use more accurate fast f64 fdiv
2021-01-21 10:51:36 -05:00
fdiv.ll
[DAGCombiner] Require ninf for division estimation
2020-06-14 22:58:22 +08:00
fdot2.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fence-barrier.ll
AMDGPU: Increase vcc liveness scan threshold
2019-10-20 17:44:17 +00:00
fence-lds-read2-write2.ll
[AMDGPU] Better selection of base offset when merging DS reads/writes
2021-02-11 17:46:09 +00:00
fetch-limits.r600.ll
…
fetch-limits.r700+.ll
…
fexp.ll
[AMDGPU] Clean up update_llc_test_checks CodeGen tests
2019-10-24 17:35:33 -04:00
ffloor.f64.ll
[AMDGPU] Fix dubious regexes with unescaped brackets. NFC.
2021-04-06 13:17:41 +01:00
ffloor.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
fix-frame-ptr-reg-copy-livein.ll
[AMDGPU] Mark epilog restores as frame-destroy
2021-02-02 10:24:37 +01:00
fix-sgpr-copies.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fix-vgpr-copies.mir
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
2019-09-11 11:16:48 +00:00
fix-wwm-vgpr-copy.ll
[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm
2021-03-03 09:33:57 +01:00
flat_atomics_i64.ll
AMDGPU: Add some missing atomics tests
2020-04-26 15:09:35 -04:00
flat_atomics.ll
AMDGPU: Add some missing atomics tests
2020-04-26 15:09:35 -04:00
flat-address-space.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
flat-error-unsupported-gpu-hsa.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
flat-for-global-subtarget-feature.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
flat-load-clustering.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
flat-offset-bug.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
flat-scratch-fold-fi.mir
[AMDGPU] SIFoldOperands: eagerly delete dead copies
2021-04-09 13:52:54 +01:00
flat-scratch-reg.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
flat-scratch.ll
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
floor.ll
…
fma-combine.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
fma.f64.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
fma.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
fmac.sdwa.ll
[AMDGPU] Enable v4f16 and above for v_pk_fma instructions
2019-07-29 08:15:10 +00:00
fmad-formation-fmul-distribute-denormal-mode.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
fmad.ll
…
fmax3.f64.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
fmax3.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmax_legacy.f16.ll
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
2019-07-11 14:45:03 +00:00
fmax_legacy.f64.ll
[AMDGPU] Optimize waitcnt insertion for flat memory operations
2020-10-20 22:55:12 +00:00
fmax_legacy.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fmax.ll
…
fmaxnum.f64.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
fmaxnum.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fmaxnum.r600.ll
AMDGPU: Split amdgcn/r600 fminnum/fmaxnum tests
2018-07-31 20:38:42 +00:00
fmed3.ll
AMDGPU: Don't form fmed3 if it will require materialization
2018-09-18 02:34:54 +00:00
fmin3.ll
[AMDGPU] Ban i8 min3 promotion.
2019-03-19 15:50:24 +00:00
fmin_fmax_legacy.amdgcn.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fmin_legacy.f16.ll
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
2019-07-11 14:45:03 +00:00
fmin_legacy.f64.ll
[AMDGPU] Optimize waitcnt insertion for flat memory operations
2020-10-20 22:55:12 +00:00
fmin_legacy.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fmin.ll
…
fminnum.f64.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fminnum.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fminnum.r600.ll
AMDGPU: Split amdgcn/r600 fminnum/fmaxnum tests
2018-07-31 20:38:42 +00:00
fmul64.ll
[AMDGPU] Switch scalarize global loads ON by default
2017-07-04 17:32:00 +00:00
fmul-2-combine-multi-use.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
fmul.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fmul.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
fmuladd.f16.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fmuladd.f32.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fmuladd.f64.ll
[NFC][AMDGPU] Improve fused fmul+fadd tests.
2020-07-31 04:00:09 +03:00
fmuladd.v2f16.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fnearbyint.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
fneg-combines.ll
[AMDGPU] Fix dubious regexes with unescaped brackets. NFC.
2021-04-06 13:17:41 +01:00
fneg-combines.si.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fneg-fabs.f16.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fneg-fabs.f64.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fneg-fabs.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fneg-fold-legalize-dag-increase-insts.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
fneg.f16.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
fneg.f64.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
fneg.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
fold_16bit_imm.mir
[AMDGPU] Add _e64 suffix to VOP3 Insts
2021-01-12 18:33:18 -05:00
fold_acc_copy_into_valu.mir
[AMDGPU] Fix illegal agpr use by VALU
2019-10-02 23:23:46 +00:00
fold-cndmask-wave32.mir
[AMDGPU] SIFoldOperands: eagerly delete dead copies
2021-04-09 13:52:54 +01:00
fold-cndmask.mir
[AMDGPU] SIFoldOperands: eagerly delete dead copies
2021-04-09 13:52:54 +01:00
fold-fi-mubuf.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
fold-fi-operand-shrink.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fold-fmul-to-neg-abs.ll
Fold fneg and fabs like multiplications
2017-06-28 20:25:50 +00:00
fold-imm-copy.mir
[AMDGPU] Fix typo in regular expression checks. NFC.
2021-04-06 12:29:48 +01:00
fold-imm-f16-f32.mir
[AMDGPU] SIFoldOperands: eagerly delete dead copies
2021-04-09 13:52:54 +01:00
fold-immediate-operand-shrink-with-carry.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fold-immediate-operand-shrink.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
fold-immediate-output-mods.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
fold-implicit-operand.mir
[AMDGPU] Add support for immediate operand for S_ENDPGM
2019-03-12 09:52:58 +00:00
fold-multiple.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
fold-operands-order.mir
[AMDGPU] SIFoldOperands: eagerly delete dead copies
2021-04-09 13:52:54 +01:00
fold-operands-remove-m0-redef.mir
AMDGPU: Erase redundant redefs of m0 in SIFoldOperands
2019-10-21 19:53:46 +00:00
fold-over-exec.mir
[AMDGPU] SIFoldOperands should not fold register acrocc the EXEC definition
2019-09-30 15:31:17 +00:00
fold-readlane.mir
[AMDGPU] SIFoldOperands: eagerly delete dead copies
2021-04-09 13:52:54 +01:00
fold-reload-into-exec.mir
[AMDGPU] Save all lanes for reserved VGPRs
2021-02-04 09:56:36 +01:00
fold-reload-into-m0.mir
[AMDGPU] Save all lanes for reserved VGPRs
2021-02-04 09:56:36 +01:00
fold-sgpr-copy.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
fold-sgpr-multi-imm.mir
AMDGPU: Fix using unencodable instructions in tests
2020-06-04 16:50:19 -04:00
fold-vgpr-copy.mir
[AMDGPU] Add _e64 suffix to VOP3 Insts
2021-01-12 18:33:18 -05:00
force-alwaysinline-lds-global-address-codegen.ll
[AMDGPU] Disable forceful inline of non-kernel functions which use LDS.
2021-04-15 09:12:56 +05:30
force-alwaysinline-lds-global-address.ll
[AMDGPU] Disable forceful inline of non-kernel functions which use LDS.
2021-04-15 09:12:56 +05:30
fp16_to_fp32.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
fp16_to_fp64.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
fp32_to_fp16.ll
[AMDGPU] Switch scalarize global loads ON by default
2017-07-04 17:32:00 +00:00
fp64-atomics-gfx90a.ll
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
fp_to_sint.f64.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
fp_to_sint.ll
[AMDGPU] Regenerate fp2int tests. NFCI.
2021-05-06 11:55:14 +01:00
fp_to_uint.f64.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
fp_to_uint.ll
[AMDGPU] Regenerate fp2int tests. NFCI.
2021-05-06 11:55:14 +01:00
fp-atomic-to-s_denormmode.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
fp-classify.ll
AMDGPU: Combine and of seto/setuo and fp_class
2018-08-10 18:58:56 +00:00
fpext-free.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fpext.f16.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fpext.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
fpow.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
fptosi.f16.ll
[AMDGPU] Select V_CVT_*16_F16 more often
2021-05-05 08:57:51 +01:00
fptoui.f16.ll
[AMDGPU] Select V_CVT_*16_F16 more often
2021-05-05 08:57:51 +01:00
fptrunc.f16.ll
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed
2021-01-04 14:44:10 -06:00
fptrunc.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
fract.f64.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fract.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
frame-index-elimination.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
frame-lowering-entry-all-sgpr-used.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
frame-lowering-fp-adjusted.mir
[AMDGPU] Remove scratch rsrc from spill pseudos
2020-11-12 15:23:37 -08:00
frame-setup-without-sgpr-to-vgpr-spills.ll
[AMDGPU] Kill temporary register after restoring
2021-04-12 14:20:03 +02:00
frem.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
fshl.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
fshr.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
fsqrt.f64.ll
[AMDGPU] Switch scalarize global loads ON by default
2017-07-04 17:32:00 +00:00
fsqrt.ll
AMDGPU/EG,CM: Implement fsqrt using recip(rsqrt(x)) instead of x * rsqrt(x)
2020-02-05 00:24:07 -05:00
fsub64.ll
[AMDGPU] Switch scalarize global loads ON by default
2017-07-04 17:32:00 +00:00
fsub.f16.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
fsub.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
ftrunc.f64.ll
[AMDGPU] Add and update scalar instructions
2018-11-29 16:05:38 +00:00
ftrunc.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
function-args.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
function-call-relocs.ll
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
function-returns.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
gds-atomic.ll
AMDGPU: Support GDS atomics
2019-07-01 17:17:45 +00:00
gep-address-space.ll
[AMDGPU] Shrink scalar AND, OR, XOR instructions
2018-12-07 15:33:21 +00:00
gfx10-vop-literal.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
gfx90a-enc.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
gfx902-without-xnack.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
gfx-callable-argument-types.ll
AMDGPU: Allow tail calls for amdgpu_gfx functions
2021-03-22 10:55:19 -04:00
gfx-callable-preserved-registers.ll
[AMDGPU] Save all lanes for reserved VGPRs
2021-02-04 09:56:36 +01:00
gfx-callable-return-types.ll
[AMDGPU] Fix large return values with amdgpu_gfx
2021-04-15 14:57:56 +02:00
global_atomics_i64.ll
[AMDGPU] Improve global SADDR selection
2021-05-05 14:44:21 -07:00
global_atomics.ll
[AMDGPU] Improve global SADDR selection
2021-05-05 14:44:21 -07:00
global_smrd_cfg.ll
[AA] Split up LocationSize::unknown()
2020-11-26 18:39:55 +01:00
global_smrd.ll
[amdgpu] Enable use of AA during codegen.
2020-10-27 09:46:23 -04:00
global-atomics-fp-wrong-subtarget.ll
AMDGPU: Restore atomic fp feature on FP atomic instruction definitions
2021-04-22 21:32:01 -04:00
global-atomics-fp.ll
[AMDGPU] Allow -amdgpu-unsafe-fp-atomics to ignore denorm mode
2021-04-08 12:46:36 -07:00
global-constant.ll
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
global-directive.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
global-extload-i16.ll
[AMDGPU] Switch scalarize global loads ON by default
2017-07-04 17:32:00 +00:00
global-load-saddr-to-vaddr.ll
[AMDGPU] Change FLAT SADDR to VADDR form in moveToVALU
2021-05-03 10:36:26 -07:00
global-saddr-atomics.gfx908.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
global-saddr-atomics.gfx1030.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
global-saddr-atomics.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
global-saddr-load.ll
[AMDGPU] Improve global SADDR selection
2021-05-05 14:44:21 -07:00
global-saddr-store.ll
[AMDGPU] Don't check for VMEM hazards on GFX10
2021-03-04 21:44:56 +00:00
global-smrd-unknown.ll
[AMDGPU] Switch AnnotateUniformValues to MemorySSA
2021-05-05 18:34:41 -07:00
global-variable-relocs.ll
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
greedy-broken-ssa-verifier-error.mir
RegAlloc: Clear isSSA
2020-10-28 12:02:16 -04:00
gv-const-addrspace.ll
[NFC] Removed unused prefixes in test/CodeGen/AMDGPU
2021-01-05 19:18:30 -08:00
gv-offset-folding.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
gws-hazards.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
half.ll
[AMDGPU] Don't cluster stores
2020-09-14 13:40:17 +01:00
hard-clauses.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
hazard-buffer-store-v-interp.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
hazard-hidden-bundle.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
hazard-in-bundle.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
hazard-inlineasm.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
hazard-kill.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
hazard-pass-ordering.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
hazard-recognizer-meta-insts.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
hazard.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
hip.extern.shared.array.ll
[amdgpu] Add codegen support for HIP dynamic shared memory.
2020-08-20 21:29:18 -04:00
hoist-cond.ll
[AMDGPU] Fix dubious regexes with unescaped brackets. NFC.
2021-04-06 13:17:41 +01:00
hsa-default-device.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-fp-mode.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-func-align.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
hsa-func.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-globals.ll
[AMDGPU] Corrected directive to use for ELF weak refs
2020-09-16 18:51:26 +03:00
hsa-group-segment.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
hsa-metadata-deduce-ro-arg-v3.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-metadata-deduce-ro-arg.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-metadata-enqueue-kernel-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-enqueue-kernel.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
hsa-metadata-from-llvm-ir-full-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-from-llvm-ir-full.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
hsa-metadata-hidden-args-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-hidden-args.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
hsa-metadata-hostcall-absent-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-hostcall-absent.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-metadata-hostcall-present-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-hostcall-present.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-metadata-images-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-images.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
hsa-metadata-invalid-ocl-version-1-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-invalid-ocl-version-1.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-metadata-invalid-ocl-version-2-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-invalid-ocl-version-2.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-metadata-invalid-ocl-version-3-v3.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-metadata-invalid-ocl-version-3.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
hsa-metadata-kernel-code-props-v3.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
hsa-metadata-kernel-code-props.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
hsa-metadata-wavefrontsize.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa-note-no-func.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
hsa.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
huge-number-operand-folds.mir
[AMDGPU] SIFoldOperands: eagerly delete dead copies
2021-04-09 13:52:54 +01:00
huge-private-buffer.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
i1_copy_phi_with_phi_incoming_value.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
i1-copies-rpo.mir
[AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks
2021-04-30 14:10:50 +01:00
i1-copy-from-loop.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
i1-copy-implicit-def.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
i1-copy-phi-uniform-branch.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
i1-copy-phi.ll
[SelectionDAG] Enhance the simplification of copyto from implicit-def.
2019-05-27 18:26:29 +00:00
i8-to-double-to-float.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
icmp64.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
icmp-select-sete-reverse-args.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
icmp.i16.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
idiv-licm.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
idot2.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
idot4s.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
idot4u.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
idot8s.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
idot8u.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
illegal-sgpr-to-vgpr-copy.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
image_ls_mipmap_zero.ll
[AMDGPU] Optimize image_[load|store]_mip
2019-06-10 15:58:51 +00:00
image-attributes.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
image-load-d16-tfe.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
image-resource-id.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
image-sample-waterfall.ll
AMDGPU: Implement waterfall loop for MIMG instructions with 256-bit SRsrc
2020-08-18 16:27:36 -07:00
image-schedule.ll
AMDGPU: Fix some outdated datalayouts in tests
2018-09-13 11:56:28 +00:00
img-nouse-adjust.ll
[AMDGPU] Allow MIMG with no uses in adjustWritemask in isel
2019-03-20 09:29:55 +00:00
imm16.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
imm.ll
[AMDGPU] Regenerate immediate constant tests
2020-02-19 18:58:44 +00:00
immv216.ll
[AMDGPU][MC][GFX9+] Corrected encoding of op_sel_hi for unused operands in VOP3P
2021-03-02 13:02:25 +03:00
implicit-def-muse.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
indirect-addressing-si-gfx9.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
indirect-addressing-si-noopt.ll
[SDAG] fold extract_vector_elt with undef index
2019-10-25 19:27:26 -04:00
indirect-addressing-si-pregfx9.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
indirect-addressing-si.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
indirect-addressing-term.ll
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
indirect-call.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
indirect-private-64.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
infer-addrpace-pipeline.ll
[NewPM] Port infer-address-spaces
2020-12-28 19:58:12 -08:00
infer-uniform-load-shader.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
infinite-loop-evergreen.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
infinite-loop.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
inline-asm.i128.ll
AMDGPU: Add even aligned VGPR/AGPR register classes
2021-02-24 14:49:37 -05:00
inline-asm.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
inline-attr.ll
[funcattrs] Add the maximal set of implied attributes to definitions
2021-04-16 14:22:19 -07:00
inline-calls.ll
AMDGPU: Enable function calls by default
2019-02-28 00:40:32 +00:00
inline-constraints.ll
[AMDGPU][CODEGEN] Added support of new inline assembler constraints
2020-07-02 17:20:15 +03:00
inline-maxbb.ll
[AMDGPU][Inliner] Remove amdgpu-inline and add a new TTI inline hook
2021-01-21 20:29:17 -08:00
inlineasm-16.ll
[AMDGPU] Inline asm - added i16, half and i128 types support
2018-06-08 16:29:04 +00:00
inlineasm-illegal-type.ll
[AMDGPU] Inline asm - added i16, half and i128 types support
2018-06-08 16:29:04 +00:00
inlineasm-packed.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
InlineAsmCrash.ll
[AMDGPU] Control num waves per EU for implicit work-group size
2020-07-01 22:53:52 -04:00
input-mods.ll
…
insert_subreg.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
insert_vector_dynelt.ll
[AMDGPU] Make bfi patterns divergence-aware
2020-09-28 10:16:51 +01:00
insert_vector_elt.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
insert_vector_elt.v2i16.ll
[AMDGPU] Simplify some RUN lines. NFC.
2021-01-28 17:57:55 +00:00
insert_vector_elt.v2i16.subtest-nosaddr.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
insert_vector_elt.v2i16.subtest-saddr.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
insert-branch-w32.mir
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
insert-skip-from-vcc.mir
[AMDGPU] Translate s_and/s_andn2 to s_mov in vcc optimisation
2020-07-17 11:48:57 +09:00
insert-skips-flat-vmem-ds.mir
[AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole
2021-03-20 11:26:42 +09:00
insert-skips-gws.mir
[AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole
2021-03-20 11:26:42 +09:00
insert-skips-ignored-insts.mir
[AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole
2021-03-20 11:26:42 +09:00
insert-subvector-unused-scratch.ll
[AMDGPU] Use ds_read/write_b96/b128 when possible for SDag
2020-08-21 12:26:31 +02:00
insert-waitcnts-callee.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
insert-waitcnts-exp.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
inserted-wait-states.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
internalize.ll
[NewPM][AMDGPU] Run InternalizePass when -amdgpu-internalize-symbols
2021-01-04 11:34:40 -08:00
invalid-addrspacecast.ll
AMDGPU: Lower addrspacecast to 32-bit constant
2020-05-08 10:46:00 -04:00
invalid-alloca.ll
[llc] Add reportError helper and canonicalize error messages
2021-01-26 15:33:37 -08:00
invariant-load-no-alias-store.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
invert-br-undef-vcc.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
ipra-regmask.ll
[AMDGPU] Introduce more scratch registers in the ABI.
2020-05-05 23:02:58 +05:30
ipra.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
jump-address.ll
[AMDGPU] change test to avoid NaN math
2018-03-19 19:26:22 +00:00
kcache-fold.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
kernarg-size.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
kernarg-stack-alignment.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
kernel-args.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
kernel-argument-dag-lowering.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-05 20:22:40 -08:00
kill-infinite-loop.ll
[AMDGPU] Rename SIInsertSkips Pass
2021-03-20 11:48:04 +09:00
known-never-nan.ll
DAG: Handle extract_vector_elt in isKnownNeverNaN
2018-09-03 14:01:03 +00:00
known-never-snan.ll
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed
2021-01-04 14:44:10 -06:00
knownbits-recursion.ll
[AMDGPU] Testcase for computeKnownBits recursion. NFC.
2017-09-01 22:25:22 +00:00
large-alloca-compute.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
large-alloca-graphics.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
large-constant-initializer.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
large-work-group-promote-alloca.ll
AMDGPU Reduce reported maximum group size to 1024
2019-11-13 06:34:28 +05:30
lcssa-optnone.ll
[AMDGPU] Run unreachable-mbb-elimination after isel to clean up PHIs.
2019-07-25 14:50:18 +00:00
lds_atomic_f32.ll
[AMDGPU] Make ds fp atomics overloadable
2020-09-23 11:39:50 -07:00
lds-alignment.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
lds-bounds.ll
AMDGPU: Fix some more incorrect check lines
2020-02-26 14:37:22 +00:00
lds-branch-vmem-hazard.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
lds-global-non-entry-func.ll
[AMDGPU] Rename "LDS lowering" pass name.
2021-04-14 20:19:53 +05:30
lds-initializer.ll
[Diagnose] Unify MCContext and LLVMContext diagnosing
2021-03-01 15:58:37 -08:00
lds-m0-init-in-loop.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
lds-misaligned-bug.ll
[AMDGPU] Only use ds_read/write_b128 for alignment >= 16
2021-04-08 08:12:05 +05:30
lds-oqap-crash.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
lds-output-queue.ll
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
2017-11-30 12:12:19 +00:00
lds-relocs.ll
ELFObjectWriter: Don't sort non-local symbols
2021-02-13 10:32:27 -08:00
lds-size.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
lds-zero-initializer.ll
[Diagnose] Unify MCContext and LLVMContext diagnosing
2021-03-01 15:58:37 -08:00
legalize-fp-load-invariant.ll
[AMDGPU] Rename pass "isel" to "amdgpu-isel"
2018-10-03 03:38:22 +00:00
legalizedag-bug-expand-setcc.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
limit-coalesce.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
limit-soft-clause-reg-pressure.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
lit.local.cfg
[NFC] Disallow unused prefixes under llvm/test/CodeGen
2021-01-11 12:32:18 -08:00
literals.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
liveness.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
llc-pipeline.ll
[AMDGPU] Switch AnnotateUniformValues to MemorySSA
2021-05-05 18:34:41 -07:00
llvm.amdgcn.alignb.ll
[AMDGPU] Add intrinsics for alignbit and alignbyte instructions
2017-06-09 19:03:00 +00:00
llvm.amdgcn.atomic.csub.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
llvm.amdgcn.atomic.dec.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
llvm.amdgcn.atomic.fadd.gfx90a.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
llvm.amdgcn.atomic.fadd.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
llvm.amdgcn.atomic.inc.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
llvm.amdgcn.ballot.i32.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
llvm.amdgcn.ballot.i64.ll
[AMDGPU][GlobalISel] Select llvm.amdgcn.ballot
2020-07-13 12:14:43 +02:00
llvm.amdgcn.buffer.atomic.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
llvm.amdgcn.buffer.load.dwordx3.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
llvm.amdgcn.buffer.load.format.d16.ll
[AMDGPU] Add v3f16/v3i16 support to SDag
2020-09-16 17:20:27 +02:00
llvm.amdgcn.buffer.load.format.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
llvm.amdgcn.buffer.load.ll
[AMDGPU] Use divergent addresses for vector loads
2021-02-23 13:33:15 +00:00
llvm.amdgcn.buffer.store.dwordx3.ll
[AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics
2019-03-22 14:58:02 +00:00
llvm.amdgcn.buffer.store.format.d16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.buffer.store.format.ll
AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests
2021-01-06 11:37:00 -05:00
llvm.amdgcn.buffer.store.ll
[AMDGPU] Add buffer/load 8/16 bit overloaded intrinsics
2019-03-19 16:07:00 +00:00
llvm.amdgcn.buffer.wbinvl1.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.buffer.wbinvl1.sc.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.buffer.wbinvl1.vol.ll
AMDGPU: Remove mayLoad/mayStore from some side effecting intrinsics
2020-06-18 14:12:19 -04:00
llvm.amdgcn.class.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.amdgcn.class.ll
AMDGPU: Make s34 the FP register
2019-07-08 19:03:38 +00:00
llvm.amdgcn.cos.f16.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.cos.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubeid.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubema.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubesc.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.cubetc.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.cvt.pk.i16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pk.u16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pknorm.i16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pknorm.u16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.amdgcn.cvt.pkrtz.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
llvm.amdgcn.dispatch.id.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
llvm.amdgcn.dispatch.ptr.ll
[amdgpu] Add the late codegen preparation pass.
2020-10-27 14:07:59 -04:00
llvm.amdgcn.div.fixup.f16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.div.fixup.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.amdgcn.div.fmas.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
llvm.amdgcn.div.scale.ll
[AMDGPU] Allow some modifiers on VOP3B instructions
2020-10-28 21:54:14 +00:00
llvm.amdgcn.ds.append.ll
AMDGPU/GlobalISel: Fix not constraining ds_append/consume operands
2020-07-26 10:17:36 -04:00
llvm.amdgcn.ds.bpermute.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
llvm.amdgcn.ds.consume.ll
AMDGPU/GlobalISel: Fix not constraining ds_append/consume operands
2020-07-26 10:17:36 -04:00
llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
[FastRA] Fix handling of bundled MIs
2020-12-21 02:10:55 -05:00
llvm.amdgcn.ds.gws.barrier.ll
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
llvm.amdgcn.ds.gws.init.ll
AMDGPU/GlobalISel: Select DS GWS intrinsics
2020-01-16 11:25:10 -05:00
llvm.amdgcn.ds.gws.sema.br.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.ds.gws.sema.p.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.ds.gws.sema.release.all.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.ds.gws.sema.v.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.ds.ordered.add.gfx10.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
llvm.amdgcn.ds.ordered.add.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
llvm.amdgcn.ds.ordered.swap.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
llvm.amdgcn.ds.permute.ll
[AMDGPU] Add a new pass to insert waitcnts. Leave under an option for testing.
2017-04-12 03:25:12 +00:00
llvm.amdgcn.ds.swizzle.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
llvm.amdgcn.exp.compr.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
llvm.amdgcn.exp.ll
[AMDGPU] Fix scheduling of exp pos4
2020-11-12 19:57:14 +00:00
llvm.amdgcn.exp.prim.ll
[AMDGPU] gfx1010 exp modifications
2019-05-08 21:23:37 +00:00
llvm.amdgcn.fcmp.ll
IR: Add immarg attribute
2019-03-12 21:02:54 +00:00
llvm.amdgcn.fdiv.fast.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.fdot2.ll
[AMDGPU] gfx1011/gfx1012 targets
2019-06-14 00:33:31 +00:00
llvm.amdgcn.fma.legacy.ll
[AMDGPU] Fix test case for D94010
2021-01-19 16:46:47 +00:00
llvm.amdgcn.fmad.ftz.f16.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
llvm.amdgcn.fmad.ftz.ll
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed
2021-01-04 14:44:10 -06:00
llvm.amdgcn.fmed3.f16.ll
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
2017-12-08 20:52:28 +00:00
llvm.amdgcn.fmed3.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
llvm.amdgcn.fmul.legacy.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
llvm.amdgcn.fract.f16.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.fract.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.frexp.exp.f16.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.frexp.exp.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.frexp.mant.f16.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.frexp.mant.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.groupstaticsize.ll
AMDGPU/GlobalISel: Select llvm.amdgcn.groupstaticsize
2020-08-18 09:28:01 -04:00
llvm.amdgcn.icmp.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.image.a16.dim.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.a16.encode.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.atomic.dim.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
llvm.amdgcn.image.d16.dim.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.image.dim.gfx90a.ll
AMDGPU: Remove special case in shouldCoalesce
2021-02-24 14:49:44 -05:00
llvm.amdgcn.image.dim.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.gather4.d16.dim.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.image.gather4.dim.ll
[AMDGPU][SDag] Add IMG init also for image_gather4 instructions
2021-04-06 14:47:20 +01:00
llvm.amdgcn.image.gather4.o.dim.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.getlod.dim.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
llvm.amdgcn.image.load.a16.d16.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.load.a16.ll
[AMDGPU] Add a16 feature to gfx10
2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.msaa.load.x.ll
[AMDGPU] Restrict image_msaa_load to MSAA dimension types
2021-03-12 09:47:24 +09:00
llvm.amdgcn.image.nsa.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
llvm.amdgcn.image.sample.a16.dim.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.sample.d16.dim.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.sample.dim.gfx90a.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
llvm.amdgcn.image.sample.dim.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.sample.g16.encode.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.sample.g16.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.sample.ltolz.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.sample.o.dim.ll
[AMDGPU] Use v3f32 type in image instructions
2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.store.a16.d16.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
llvm.amdgcn.image.store.a16.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
llvm.amdgcn.implicit.buffer.ptr.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
llvm.amdgcn.implicitarg.ptr.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
llvm.amdgcn.init.exec.ll
[AMDGPU] Fix llvm.amdgcn.init.exec and frame materialization
2021-01-25 08:31:17 +09:00
llvm.amdgcn.init.exec.wave32.ll
AMDGPU/GlobalISel: Add support for init.exec intrinsics
2019-10-01 02:07:25 +00:00
llvm.amdgcn.interp.f16.ll
AMDGPU: Use CopyToReg for interp intrinsic lowering
2019-10-21 19:53:49 +00:00
llvm.amdgcn.interp.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.intersect_ray.ll
[AMDGPU] gfx1030 RT support
2020-09-16 11:40:58 -07:00
llvm.amdgcn.is.private.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.is.shared.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
llvm.amdgcn.kernarg.segment.ptr.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
llvm.amdgcn.kill.ll
[AMDGPU] Move kill lowering to WQM pass and add live mask tracking
2021-02-11 20:31:29 +09:00
llvm.amdgcn.ldexp.f16.ll
[AMDGPU] Switch scalarize global loads ON by default
2017-07-04 17:32:00 +00:00
llvm.amdgcn.ldexp.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.lerp.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.log.clamp.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.mbcnt.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
llvm.amdgcn.mfma.bf16.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
llvm.amdgcn.mfma.gfx90a.ll
[AMDGPU] Fix typo in regular expression checks. NFC.
2021-04-06 12:29:48 +01:00
llvm.amdgcn.mfma.i8.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
llvm.amdgcn.mfma.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
llvm.amdgcn.mov.dpp8.ll
[AMDGPU] gfx1010 dpp16 and dpp8
2019-06-12 18:02:41 +00:00
llvm.amdgcn.mov.dpp.ll
[AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3
2021-02-22 14:59:40 +03:00
llvm.amdgcn.mqsad.pk.u16.u8.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
llvm.amdgcn.mqsad.u32.u8.ll
AMDGPU: Use correct register names in inline assembly
2017-06-08 19:03:20 +00:00
llvm.amdgcn.msad.u8.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.mul.i24.ll
AMDGPU: Add 24-bit mul intrinsics
2019-07-15 17:50:31 +00:00
llvm.amdgcn.mul.u24.ll
AMDGPU: Add 24-bit mul intrinsics
2019-07-15 17:50:31 +00:00
llvm.amdgcn.permlane.ll
AMDGPU/GlobalISel: Select permlane16/permlanex16
2020-01-29 17:55:31 -05:00
llvm.amdgcn.ps.live.ll
[AMDGPU] Added -mcpu=tahiti to 3 tests. NFC.
2021-01-25 15:50:59 -08:00
llvm.amdgcn.qsad.pk.u16.u8.ll
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
2019-10-14 12:01:10 +00:00
llvm.amdgcn.queue.ptr.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
llvm.amdgcn.raw.buffer.atomic.fadd.ll
[AMDGPU] Unify intrinsic ret/nortn interface
2020-09-15 15:26:42 -07:00
llvm.amdgcn.raw.buffer.atomic.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.load.format.d16.ll
[AMDGPU] Add v3f16/v3i16 support to SDag
2020-09-16 17:20:27 +02:00
llvm.amdgcn.raw.buffer.load.format.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.load.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.store.format.d16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.raw.buffer.store.format.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.store.ll
[AMDGPU] Extend buffer intrinsics with swizzling
2019-10-02 17:22:36 +00:00
llvm.amdgcn.raw.tbuffer.load.d16.ll
[AMDGPU] Add v3f16/v3i16 support to SDag
2020-09-16 17:20:27 +02:00
llvm.amdgcn.raw.tbuffer.load.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
llvm.amdgcn.raw.tbuffer.store.d16.ll
[AMDGPU] Add v3f16/v3i16 support to SDag
2020-09-16 17:20:27 +02:00
llvm.amdgcn.raw.tbuffer.store.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.rcp.f16.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.rcp.legacy.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.rcp.ll
AMDGPU: Remove v_rsq_f64 patterns
2021-01-21 10:51:36 -05:00
llvm.amdgcn.readfirstlane.ll
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
llvm.amdgcn.readlane.ll
AMDGPU: Relax 32-bit SGPR register class
2019-10-18 18:26:37 +00:00
llvm.amdgcn.rsq.clamp.ll
[AMDGPU] Fix typo in regular expression checks. NFC.
2021-04-06 12:29:48 +01:00
llvm.amdgcn.rsq.f16.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.rsq.legacy.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.rsq.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.s.barrier.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
llvm.amdgcn.s.buffer.load.ll
AMDGPU: Fix broken check lines
2020-04-02 18:52:49 -04:00
llvm.amdgcn.s.dcache.inv.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.dcache.inv.vol.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.dcache.wb.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.dcache.wb.vol.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
llvm.amdgcn.s.decperflevel.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.s.get.waveid.in.workgroup.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
llvm.amdgcn.s.getpc.ll
Resubmit r303859 with test fixed.
2017-05-26 20:38:26 +00:00
llvm.amdgcn.s.getreg.ll
AMDGPU/GlobalISel: Fix selecting llvm.amdgcn.s.getreg
2020-07-28 21:34:50 -04:00
llvm.amdgcn.s.incperflevel.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.s.memrealtime.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.s.memtime.ll
Revert "Revert "[AMDGPU] Restore the s_memtime instruction in gfx1030""
2021-03-06 09:00:01 +00:00
llvm.amdgcn.s.sethalt.ll
[AMDGPU] New intrinsic void llvm.amdgcn.s.sethalt(i32)
2021-03-01 14:30:23 +00:00
llvm.amdgcn.s.setreg.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
llvm.amdgcn.s.sleep.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.s.waitcnt.ll
AMDGPU: s_waitcnt field should be treated as unsigned
2019-07-11 23:42:57 +00:00
llvm.amdgcn.sad.hi.u8.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.sad.u8.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.sad.u16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.sbfe.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.sdot2.ll
[AMDGPU] gfx908 dot instruction support
2019-07-11 00:00:27 +00:00
llvm.amdgcn.sdot4.ll
[AMDGPU] gfx1031 target
2020-08-05 12:36:26 -07:00
llvm.amdgcn.sdot8.ll
[AMDGPU] gfx1031 target
2020-08-05 12:36:26 -07:00
llvm.amdgcn.sendmsg.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
llvm.amdgcn.set.inactive.ll
[AMDGPU] Mark V_SET_INACTIVE as defining SCC
2021-01-29 09:46:41 +09:00
llvm.amdgcn.sffbh.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
llvm.amdgcn.sin.f16.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.amdgcn.sin.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.softwqm.ll
[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm
2021-03-03 09:33:57 +01:00
llvm.amdgcn.sqrt.f16.ll
AMDGPU: Add llvm.amdgcn.sqrt intrinsic
2020-06-26 15:07:07 -04:00
llvm.amdgcn.sqrt.ll
AMDGPU: Add llvm.amdgcn.sqrt intrinsic
2020-06-26 15:07:07 -04:00
llvm.amdgcn.struct.buffer.atomic.fadd.ll
[AMDGPU] Unify intrinsic ret/nortn interface
2020-09-15 15:26:42 -07:00
llvm.amdgcn.struct.buffer.atomic.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.load.format.d16.ll
[AMDGPU] Add v3f16/v3i16 support to SDag
2020-09-16 17:20:27 +02:00
llvm.amdgcn.struct.buffer.load.format.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.load.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.store.format.d16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.buffer.store.format.ll
[AMDGPU] Allow struct.buffer.*.format intrinsics to accept i32
2020-03-11 08:20:32 +09:00
llvm.amdgcn.struct.buffer.store.ll
AMDGPU: Correct behavior of f16/i16 non-format store intrinsics
2019-08-05 14:57:59 +00:00
llvm.amdgcn.struct.tbuffer.load.d16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.tbuffer.load.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
llvm.amdgcn.struct.tbuffer.store.d16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.struct.tbuffer.store.ll
[AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier
2020-07-24 16:41:03 +03:00
llvm.amdgcn.tbuffer.load.d16.ll
AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests
2021-01-06 11:37:00 -05:00
llvm.amdgcn.tbuffer.load.dwordx3.ll
AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests
2021-01-06 11:37:00 -05:00
llvm.amdgcn.tbuffer.load.ll
AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests
2021-01-06 11:37:00 -05:00
llvm.amdgcn.tbuffer.store.d16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.tbuffer.store.dwordx3.ll
AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests
2021-01-06 11:37:00 -05:00
llvm.amdgcn.tbuffer.store.ll
AMDGPU: Explicitly use SelectionDAG in legacy intrinsic tests
2021-01-06 11:37:00 -05:00
llvm.amdgcn.trig.preop.ll
[AMDGPU] Switch scalarize global loads ON by default
2017-07-04 17:32:00 +00:00
llvm.amdgcn.ubfe.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
llvm.amdgcn.udot2.ll
[AMDGPU] Added udot2 op_sel test. NFC.
2021-04-09 12:19:42 -07:00
llvm.amdgcn.udot4.ll
[AMDGPU] gfx1011/gfx1012 targets
2019-06-14 00:33:31 +00:00
llvm.amdgcn.udot8.ll
[AMDGPU] gfx1011/gfx1012 targets
2019-06-14 00:33:31 +00:00
llvm.amdgcn.unreachable.ll
Fix test from polluting the source tree
2017-04-22 07:53:40 +00:00
llvm.amdgcn.update.dpp.ll
[AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3
2021-02-22 14:59:40 +03:00
llvm.amdgcn.wave.barrier.ll
AMDGPU: wave_barrier is not isBarrier
2019-03-27 15:54:45 +00:00
llvm.amdgcn.wavefrontsize.ll
[NewPM][AMDGPU] Pass TargetMachine to AMDGPUSimplifyLibCallsPass
2021-01-04 13:48:09 -08:00
llvm.amdgcn.workgroup.id.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.amdgcn.workitem.id.ll
AMDGPU: Fix checks in llvm.amdgcn.workitem.id.ll
2021-02-18 11:56:15 -05:00
llvm.amdgcn.wqm.demote.ll
[AMDGPU] Fix WQM failure with single block inactive demote
2021-05-06 21:02:26 +09:00
llvm.amdgcn.wqm.vote.ll
[AMDGPU] Move kill lowering to WQM pass and add live mask tracking
2021-02-11 20:31:29 +09:00
llvm.amdgcn.writelane.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.ceil.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.cos.f16.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
llvm.cos.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.dbg.value.ll
[DebugInfo] Stop changing labels for register-described parameter DBG_VALUEs
2019-02-13 09:34:07 +00:00
llvm.exp2.f16.ll
[AMDGPU] Fixed some instructions latencies
2018-03-30 16:19:13 +00:00
llvm.exp2.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
llvm.floor.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
llvm.fma.f16.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
llvm.fmuladd.f16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.log2.f16.ll
AMDGPU: Cleanup subtarget features
2017-08-07 14:58:04 +00:00
llvm.log2.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
llvm.log10.f16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.log10.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.log.f16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.log.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.maxnum.f16.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
llvm.memcpy.ll
[ANDGPU] getMemOperandsWithOffset: support BUF non-stack-access instructions with resource but no vaddr
2020-02-03 22:49:30 +00:00
llvm.minnum.f16.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
llvm.mulo.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
llvm.pow-gfx9.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
llvm.pow.ll
…
llvm.powi.ll
AMDGPU: Fix promoting f16 fpowi with legal f16
2020-07-17 11:29:05 -04:00
llvm.r600.cube.ll
AMDGPU: Remove llvm.AMDGPU.cube intrinsic
2017-02-16 19:09:04 +00:00
llvm.r600.dot4.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.r600.group.barrier.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.r600.read.local.size.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
llvm.r600.recipsqrt.clamped.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.r600.recipsqrt.ieee.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.r600.tex.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.rint.f16.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.rint.f64.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
llvm.rint.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
llvm.round.f64.ll
[NFC][Test] Format the test with script update_llc_test_checks.py
2020-08-07 10:22:38 +00:00
llvm.round.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
llvm.sin.f16.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
llvm.sin.ll
[AMDGPU] Propagate fast-math flags when lowering FSIN and FCOS
2020-05-31 05:21:55 +01:00
llvm.sqrt.f16.ll
[AMDGPU] Fixed some instructions latencies
2018-03-30 16:19:13 +00:00
llvm.trunc.f16.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
lo16-32bit-physreg-copy.mir
[AMDGPU] fix copies between 32 and 16 bit
2020-05-04 08:54:22 -07:00
lo16-hi16-illegal-copy.mir
[AMDGPU] Drop 16 bit subreg suffixes on print
2020-05-06 08:14:10 -07:00
lo16-hi16-physreg-copy.mir
[AMDGPU] copyPhysReg() for 16 bit SGPR subregs
2020-04-17 11:59:39 -07:00
lo16-lo16-physreg-copy-agpr.mir
[AMDGPU] Define AGPR subregs
2020-04-28 15:30:43 -07:00
lo16-lo16-physreg-copy-sgpr.mir
[AMDGPU] copyPhysReg() for 16 bit SGPR subregs
2020-04-17 11:59:39 -07:00
load-constant-f32.ll
[AMDGPU] Increased vector length for global/constant loads.
2018-03-07 17:09:18 +00:00
load-constant-f64.ll
[AMDGPU] Increased vector length for global/constant loads.
2018-03-07 17:09:18 +00:00
load-constant-i1.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
load-constant-i8.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
load-constant-i16.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
load-constant-i32.ll
[AMDGPU] gfx908 mfma support
2019-07-11 21:19:33 +00:00
load-constant-i64.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
load-global-f32.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
load-global-f64.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
load-global-i1.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
load-global-i8.ll
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
2018-07-11 20:25:49 +00:00
load-global-i16.ll
[VirtRegRewriter] Insert missing killed flags when tracking subregister liveness
2021-03-03 12:02:04 -05:00
load-global-i32.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
load-global-i64.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
load-hi16.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
load-input-fold.ll
AMDGPU: Remove llvm.AMDGPU.rsq intrinsic
2017-02-16 19:08:58 +00:00
load-lo16.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
load-local-f32-no-ds128.ll
AMDGPU: Add a missing test for the 128-bit local addr space option
2018-05-15 21:41:57 +00:00
load-local-f32.ll
[AMDGPU] Use ds_read/write_b96/b128 when possible for SDag
2020-08-21 12:26:31 +02:00
load-local-f64.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
load-local-i1.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
load-local-i8.ll
[AMDGPU] Use ds_read/write_b96/b128 when possible for SDag
2020-08-21 12:26:31 +02:00
load-local-i16.ll
[AMDGPU] Use ds_read/write_b96/b128 when possible for SDag
2020-08-21 12:26:31 +02:00
load-local-i32.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
load-local-i64.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
load-local-redundant-copies.ll
[AMDGPU] Prefer SplitVectorLoad/Store over expandUnalignedLoad/Store
2020-10-08 10:17:15 +02:00
load-local.96.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
load-local.128.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
load-select-ptr.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
load-weird-sizes.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
local-64.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
local-atomics64.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
local-atomics-fp.ll
[AMDGPU] Limit memory scope for scratch, LDS and GDS
2021-02-14 17:34:12 +00:00
local-atomics.ll
Allow FP types for atomicrmw xchg
2019-01-17 10:49:01 +00:00
local-memory.amdgcn.ll
[AMDGPU] Don't cluster stores
2020-09-14 13:40:17 +01:00
local-memory.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-06 09:34:11 -08:00
local-memory.r600.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
local-stack-alloc-block-sp-reference.ll
[AMDGPU] Remove unused tmp register
2021-02-02 17:17:54 +01:00
local-stack-slot-offset.ll
[AMDGPU] Remove FeatureVGPRSpilling
2018-10-31 18:54:06 +00:00
loop_break.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
loop_exit_with_xor.ll
AMDGPU: Update tests to use modern buffer intrinsics
2020-01-16 13:49:43 -05:00
loop_header_nopred.mir
[AMDGPU] Remove SI_MASK_BRANCH
2021-03-09 09:13:23 +08:00
loop-address.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
loop-idiom.ll
[BasicAA] Rename deprecated -basicaa to -basic-aa
2020-06-26 20:41:37 -07:00
loop-live-out-copy-undef-subrange.ll
RegisterCoalescer: Prune undef subranges from copy pairs in loops
2021-02-03 13:42:53 -05:00
loop-prefetch.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
lower-control-flow-other-terminators.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
lower-kernargs.ll
Use unary CreateShuffleVector if possible
2020-12-30 22:36:08 +09:00
lower-mem-intrinsics-threshold.ll
AMDGPU: Add flag to control mem intrinsic expansion
2020-02-03 14:26:01 -08:00
lower-mem-intrinsics.ll
AMDGPU: Implement getMemcpyLoopLoweringType
2020-03-30 22:21:01 +01:00
lower-module-lds-constantexpr.ll
[amdgpu] Implement lower function LDS pass
2021-03-15 15:24:01 +00:00
lower-module-lds-inactive.ll
[amdgpu] Implement lower function LDS pass
2021-03-15 15:24:01 +00:00
lower-module-lds-indirect.ll
[amdgpu] Implement lower function LDS pass
2021-03-15 15:24:01 +00:00
lower-module-lds-used-list.ll
[amdgpu] Implement lower function LDS pass
2021-03-15 15:24:01 +00:00
lower-module-lds.ll
[amdgpu] Implement lower function LDS pass
2021-03-15 15:24:01 +00:00
lower-range-metadata-intrinsic-call.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
lower-term-opcodes.mir
[AMDGPU] Fix lowering of S_MOV_{B32,B64}_term
2020-11-10 12:16:31 +09:00
lshl64-to-32.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
lshr.v2i16.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
machine-cse-commute-target-flags.mir
AMDGPU: Support commuting register and global operand
2020-07-01 13:59:13 -04:00
machinelicm-convergent.mir
Prevent LICM and machineLICM from hoisting convergent operations
2020-11-06 10:26:39 -08:00
macro-fusion-cluster-vcc-uses.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
mad24-get-global-id.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
mad_64_32.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
mad_int24.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
mad_uint24.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
mad-combine.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
mad-mix-hi.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
mad-mix-lo.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
mad-mix.ll
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed
2021-01-04 14:44:10 -06:00
mad.u16.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
madak-inline-constant.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
madak.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
madmk.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
mai-hazards-gfx90a.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
mai-hazards.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
mai-inline.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
max3.ll
[AMDGPU] Ban i8 min3 promotion.
2019-03-19 15:50:24 +00:00
max-literals.ll
…
max-sgprs.ll
[AMDGPU] gfx1010 VOP2 changes
2019-04-26 16:37:51 +00:00
max.i16.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
max.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
mcp-overlap-after-propagation.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
med3-no-simplify.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
mem-builtins.ll
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
memcpy-fixed-align.ll
[AMDGPU] Enable multi-dword flat scratch load/stores
2020-11-12 13:38:56 -08:00
memcpy-inline-fails.ll
Revert "Disable memcpy-inline-fails.ll for windows"
2020-03-16 16:03:39 +01:00
memory_clause.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
memory_clause.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
memory-legalizer-atomic-insert-end.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
memory-legalizer-fence.ll
[AMDGPU] Update gfx90a memory model support
2021-04-07 22:17:58 +00:00
memory-legalizer-flat-agent.ll
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
memory-legalizer-flat-nontemporal.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
memory-legalizer-flat-singlethread.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-flat-system.ll
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
memory-legalizer-flat-volatile.ll
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
memory-legalizer-flat-wavefront.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-flat-workgroup.ll
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
memory-legalizer-global-agent.ll
AMDGPU: Use kill instruction to hint soft clause live ranges
2021-02-26 18:26:40 -05:00
memory-legalizer-global-nontemporal.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-global-singlethread.ll
AMDGPU: Use kill instruction to hint soft clause live ranges
2021-02-26 18:26:40 -05:00
memory-legalizer-global-system.ll
[AMDGPU] Update gfx90a memory model support
2021-04-07 22:17:58 +00:00
memory-legalizer-global-volatile.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
memory-legalizer-global-wavefront.ll
AMDGPU: Use kill instruction to hint soft clause live ranges
2021-02-26 18:26:40 -05:00
memory-legalizer-global-workgroup.ll
AMDGPU: Use kill instruction to hint soft clause live ranges
2021-02-26 18:26:40 -05:00
memory-legalizer-invalid-addrspace.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
memory-legalizer-invalid-syncscope.ll
[AMDGPU] gfx1010 memory legalizer
2019-05-06 21:57:02 +00:00
memory-legalizer-local-agent.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-local-nontemporal.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-local-singlethread.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-local-system.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-local-volatile.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
memory-legalizer-local-wavefront.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-local-workgroup.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-local.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
memory-legalizer-multiple-mem-operands-atomics.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
memory-legalizer-private-nontemporal.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
memory-legalizer-private-volatile.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
memory-legalizer-region.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
memory-legalizer-store-infinite-loop.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
merge-image-load-gfx10.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
merge-image-load.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
merge-image-sample-gfx10.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
merge-image-sample.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
merge-load-store-agpr.mir
AMDGPU: Add even aligned VGPR/AGPR register classes
2021-02-24 14:49:37 -05:00
merge-load-store-physreg.mir
AMDGPU: Remove unnecessary IR from test
2019-10-14 18:30:29 +00:00
merge-load-store-vreg.mir
[AMDGPU] Better selection of base offset when merging DS reads/writes
2021-02-11 17:46:09 +00:00
merge-load-store.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
merge-m0.mir
[AMDGPU] Remove gds operand from ds_gws_* MachineInstrs
2020-10-29 15:04:23 +00:00
merge-out-of-order-ldst.ll
[AMDGPU] Fix crash in SILoadStoreOptimizer
2020-04-02 10:26:47 -07:00
merge-out-of-order-ldst.mir
[AMDGPU] Fix crash in SILoadStoreOptimizer
2020-04-02 10:26:47 -07:00
merge-store-crash.ll
AMDGPU: Convert some tests to use new buffer intrinsics
2020-07-30 10:30:43 -04:00
merge-store-usedef.ll
AMDGPU: Convert some tests to use new buffer intrinsics
2020-07-30 10:30:43 -04:00
merge-stores.ll
[AMDGPU] Add alignment check for v3 to v4 load type promotion
2020-11-01 12:05:34 +05:30
merge-tbuffer.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
mesa3d.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
mesa_regression.ll
Fix for regression after Global Load Scalarization patch
2016-12-15 15:17:19 +00:00
mfma-loop.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
min3.ll
[AMDGPU] Ban i8 min3 promotion.
2019-03-19 15:50:24 +00:00
min.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
mir-print-dead-csr-fi.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
misched-killflags.mir
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
missing-store.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
mixed_wave32_wave64.ll
[AMDGPU] gfx10 tests. NFC.
2019-06-20 16:29:40 +00:00
mixed-wave32-wave64.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
mode-register.mir
[AMDGPU] Avoid redundant mode register writes
2020-06-24 14:11:29 +01:00
move-addr64-rsrc-dead-subreg-writes.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
move-load-addr-to-valu.mir
[AMDGPU] Change FLAT Scratch SADDR to VADDR form in moveToVALU
2021-05-03 10:57:14 -07:00
move-to-valu-atomicrmw.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
move-to-valu-worklist.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
movreld-bug.ll
[AMDGPU] Make movreld-bug test case more robust
2020-09-11 10:25:29 +01:00
movrels-bug.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
mubuf-legalize-operands.ll
[AMDGPU] Don't check for VMEM hazards on GFX10
2021-03-04 21:44:56 +00:00
mubuf-legalize-operands.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
mubuf-offset-private.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
mubuf-shader-vgpr.ll
AMDGPU: Update tests to use modern buffer intrinsics
2020-01-16 13:49:43 -05:00
mubuf.ll
[AMDGPU] Fix typo in regular expression checks. NFC.
2021-04-06 12:29:48 +01:00
mul24-pass-ordering.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
mul_int24.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
mul_uint24-amdgcn.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
mul_uint24-r600.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
mul.i16.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
mul.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
multi-divergent-exit-region.ll
[AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree
2021-01-02 01:01:20 +03:00
multi-dword-vgpr-spill.ll
[AMDGPU] Use multi-dword flat scratch for spilling
2020-12-14 14:19:29 -08:00
multilevel-break.ll
[AMDGPU][NFC] Update auto-gen test
2021-04-23 16:33:16 +02:00
nand.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
need-fp-from-csr-vgpr-spill.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
nested-calls.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
nested-loop-conditions.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
no-bundle-asm.ll
AMDGPU: Do not bundle inline asm
2020-06-14 13:24:50 -04:00
no-hsa-graphics-shaders.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
no-initializer-constant-addrspace.ll
[llvm-readobj] - For SHT_REL relocations, don't display an addend.
2020-12-14 12:03:00 +03:00
no-remat-indirect-mov.mir
AMDGPU: Don't run indexing mode switches with exec = 0
2020-06-02 13:47:48 -04:00
no-shrink-extloads.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
non-entry-alloca.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
noop-shader-O0.ll
[AMDGPU] Remove FeatureVGPRSpilling
2018-10-31 18:54:06 +00:00
nop-data.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
nor.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
not-scalarize-volatile-load.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
nsa-reassign.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
nsa-reassign.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
nsa-vmem-hazard.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
nullptr.ll
AMDGPU: Fix wrong null value for private address space
2020-05-26 16:35:13 -04:00
occupancy-levels.ll
[AMDGPU] Add occupancy level tests for GFX10.3. NFC.
2020-12-08 14:15:01 +00:00
offset-split-flat.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
offset-split-global.ll
[AMDGPU] Improve global SADDR selection
2021-05-05 14:44:21 -07:00
omod-nsz-flag.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
omod.ll
[AMDGPU] Enable output modifiers for double precision instructions
2021-04-01 10:08:17 -04:00
opencl-image-metadata.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
opencl-printf-no-hostcall.ll
[AMDGPU] add support for hostcall buffer pointer as hidden kernel argument
2019-11-20 15:53:55 +05:30
opencl-printf.ll
[NewPM][AMDGPU] Port amdgpu-printf-runtime-binding
2021-01-04 12:25:50 -08:00
operand-folding.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
operand-spacing.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
opt_exec_copy_fold.mir
[AMDGPU] SIOptimizeExecMaskingPreRA should check constant bus constraint when folds EXEC copy
2021-03-24 14:14:13 +03:00
opt-pipeline.ll
[PassManager][PhaseOrdering] lower expects before running simplifyCFG
2021-04-12 15:07:53 -04:00
opt-sgpr-to-vgpr-copy.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
optimize-exec-copies-extra-insts-after-copy.mir
AMDGPU: Optimize copies to exec with other insts after exec def
2020-07-28 21:34:50 -04:00
optimize-exec-mask-pre-ra-loop-phi.mir
AMDGPU: Check for other defs when folding conditions into s_andn2_b64
2020-07-28 16:36:23 -04:00
optimize-exec-masking-pre-ra.mir
[AMDGPU] Remove SI_MASK_BRANCH
2021-03-09 09:13:23 +08:00
optimize-exec-masking-strip-terminator-bits.mir
AMDGPU: Don't assume there is only one terminator copy
2020-07-28 20:22:38 -04:00
optimize-if-exec-masking.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
optimize-negated-cond-exec-masking-wave32.mir
[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
2020-07-14 12:53:43 +09:00
optimize-negated-cond-exec-masking.mir
[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
2020-07-14 12:53:43 +09:00
optimize-negated-cond.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
or3.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
or.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
pack.v2f16.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
pack.v2i16.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
packed-fp32.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
packed-op-sel.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
packetizer.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
pal-simple-indirect-call.ll
[AMDGPU] Do not annotate features for graphics
2021-05-03 10:33:11 +02:00
pal-userdata-regs.ll
[AMDGPU] Fixed incorrect PAL metadata register naming
2020-05-21 22:13:19 +01:00
parallelandifcollapse.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
parallelorifcollapse.ll
fix typos in comments; NFC
2017-07-16 08:11:56 +00:00
partial-sgpr-to-vgpr-spills.ll
[AMDGPU] Save VGPR of whole wave when spilling
2021-04-12 11:01:38 +02:00
partial-shift-shrink.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
partially-dead-super-register-immediate.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
peephole-opt-regseq-removal.mir
[PeepholeOpt] Don't stop simplifying copies on sequence of subregs
2019-03-27 17:27:56 +00:00
pei-build-spill-partial-agpr.mir
[AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks
2021-04-30 14:10:50 +01:00
pei-build-spill.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
pei-reg-scavenger-position.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
pei-scavenge-sgpr-carry-out.mir
[AMDGPU] Fix typo in implicit operand lists
2021-04-23 15:44:17 +01:00
pei-scavenge-sgpr-gfx9.mir
[AMDGPU] Fix typo in implicit operand lists
2021-04-23 15:44:17 +01:00
pei-scavenge-sgpr.mir
[AMDGPU] Fix typo in implicit operand lists
2021-04-23 15:44:17 +01:00
pei-scavenge-vgpr-spill.mir
[AMDGPU] Unify spill code
2021-04-12 11:19:08 +02:00
perfhint.ll
[AMDGPU] Add some missing check prefixes and tweak test
2020-07-17 12:57:47 +01:00
permute.ll
[AMDGPU] Add ISD::FSHR -> ALIGNBIT support
2020-03-12 20:16:57 +00:00
phi-elimination-assertion.mir
[AMDGPU]: PHI Elimination hooks added for custom COPY insertion. Fixed
2019-09-17 09:08:58 +00:00
phi-elimination-end-cf.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
phi-vgpr-input-moveimm.mir
[AMDGPU] Fix formatting in MIR tests
2020-07-02 10:27:34 +01:00
pk_max_f16_literal.ll
[AMDGPU] gfx1010 allows VOP3 to have a literal
2019-05-02 04:01:39 +00:00
post-ra-sched-kill-bundle-use-inst.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
post-ra-sched-reset.mir
[AMDGPU] Add Reset function to GCNHazardRecognizer
2020-10-28 16:32:32 -07:00
post-ra-soft-clause-dbg-info.ll
AMDGPU: Fix debug info handling in post-RA bundler
2021-02-16 10:42:06 -05:00
postra-bundle-memops.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
postra-machine-sink.mir
[AMDGPU] Fixed lane mask in test. NFC.
2020-04-15 15:26:53 -07:00
postra-norename.mir
[MachineOperand][Target] MachineOperand::isRenamable semantics changes
2018-02-23 18:25:08 +00:00
power-sched-no-instr-sunit.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
predicate-dp4.ll
…
predicates.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
preserve-hi16.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
print-mir-custom-pseudo.ll
[AMDGPU] Implement mir parseCustomPseudoSourceValue
2021-01-22 11:24:08 +01:00
private-access-no-objects.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
private-element-size.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
private-memory-atomics.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
private-memory-r600.ll
[AMDGPU, test] Fix use of undef FileCheck var
2021-04-08 09:42:59 +01:00
promote-alloca-addrspacecast.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
promote-alloca-array-aggregate.ll
AMDGPU: Fix assert on alloca of array of struct
2017-09-14 18:02:29 +00:00
promote-alloca-array-allocation.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
promote-alloca-bitcast-function.ll
[AMDGPU] Add a pass to promote bitcast calls
2018-10-26 13:18:36 +00:00
promote-alloca-calling-conv.ll
AMDGPU: Remove amdgpu-max-work-group-size attribute
2019-06-05 20:32:32 +00:00
promote-alloca-globals.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
promote-alloca-invariant-markers.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
promote-alloca-lifetime.ll
AMDGPU: Fix iterator crash in AMDGPUPromoteAlloca
2019-06-18 12:23:44 +00:00
promote-alloca-mem-intrinsics.ll
[AMDGPU] Fix promote alloca with double use in a same insn
2021-02-11 11:42:25 -08:00
promote-alloca-no-opts.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
promote-alloca-padding-size-estimate.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
promote-alloca-pointer-array.ll
[AMDGPU] Fixed promote alloca with ptr/int casts
2020-06-10 11:46:57 -07:00
promote-alloca-stored-pointer-value.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
promote-alloca-to-lds-constantexpr-use.ll
[AMDGPU] Rename "LDS lowering" pass name.
2021-04-14 20:19:53 +05:30
promote-alloca-to-lds-icmp.ll
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
promote-alloca-to-lds-phi.ll
[NFC] GetUnderlyingObject -> getUnderlyingObject
2020-07-30 21:08:24 -07:00
promote-alloca-to-lds-select.ll
[ValueTracking, BasicAA] Don't simplify instructions
2020-06-21 16:31:07 +02:00
promote-alloca-unhandled-intrinsic.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
promote-alloca-vector-to-vector.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
promote-alloca-volatile.ll
AMDGPU/SI: Don't promote to vector if the load/store is volatile.
2017-05-12 20:31:12 +00:00
promote-constOffset-to-imm-gfx10.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
promote-constOffset-to-imm.ll
[AMDGPU] SIFoldOperands: eagerly delete dead copies
2021-04-09 13:52:54 +01:00
promote-constOffset-to-imm.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
promote-vect3-load.ll
[AMDGPU] Add alignment check for v3 to v4 load type promotion
2020-11-01 12:05:34 +05:30
propagate-attributes-bitcast-function.ll
[AMDGPU] Fix offset for REL32_HI relocs
2020-09-02 10:55:55 +01:00
propagate-attributes-clone.ll
[NewPM][AMDGPU] Port amdgpu-propagate-attributes-early/late
2021-01-04 11:53:37 -08:00
propagate-attributes-flat-work-group-size.ll
[NewPM][AMDGPU] Port amdgpu-propagate-attributes-early/late
2021-01-04 11:53:37 -08:00
propagate-attributes-single-set.ll
[NewPM][AMDGPU] Port amdgpu-propagate-attributes-early/late
2021-01-04 11:53:37 -08:00
ptr-arg-dbg-value.ll
[MCAsmInfo] Support UsesCFIForDebug for targets with no exception handling
2021-05-06 04:53:45 +05:30
ptrmask.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
pv-packing.ll
…
pv.ll
AMDGPU: Remove llvm.AMDGPU.clamp intrinsic
2017-02-21 23:46:04 +00:00
r600-constant-array-fixup.ll
[llvm-readobj] - For SHT_REL relocations, don't display an addend.
2020-12-14 12:03:00 +03:00
r600-encoding.ll
…
r600-export-fix.ll
[AMDGPU] Automatically generate various tests. NFC
2019-08-23 17:58:49 +00:00
r600-infinite-loop-bug-while-reorganizing-vector.ll
AMDGPU: Remove llvm.AMDGPU.cube intrinsic
2017-02-16 19:09:04 +00:00
r600-legalize-umax-bug.ll
[DAG] SimplifyDemandedBits - use KnownBits comparisons to remove ISD::UMIN/UMAX ops
2021-01-18 10:29:23 +00:00
r600.add.ll
AMDGPU: Select VOP3 form of add
2019-05-08 22:09:57 +00:00
r600.alu-limits.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
r600.amdgpu-alias-analysis.ll
[AMDGPU] Add an experimental buffer fat pointer address space.
2019-03-18 14:44:28 +00:00
r600.bitcast.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
r600.extract-lowbits.ll
AMDGPU: Stop trying to extend arguments for clover
2018-07-28 12:34:25 +00:00
r600.func-alignment.ll
AMDGPU/R600: Make sure functions are cacheline aligned
2018-05-31 04:08:08 +00:00
r600.global_atomics.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
r600.private-memory.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
r600.sub.ll
AMDGPU: Select VOP3 form of sub
2019-05-03 15:37:07 +00:00
r600.work-item-intrinsics.ll
AMDGPU/R600: Convert kernel param loads to use PARAM_I_ADDRESS
2018-08-01 18:36:07 +00:00
r600cfg.ll
…
rcp_iflag.ll
AMDGPU: Remove denormal subtarget features
2020-04-02 17:17:12 -04:00
rcp-pattern.ll
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed
2021-01-04 14:44:10 -06:00
read_register.ll
AMDGPU: Adjust test so it will work with GlobalISel
2019-12-27 19:37:39 -05:00
read-register-invalid-subtarget.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
read-register-invalid-type-i32.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
read-register-invalid-type-i64.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
readcyclecounter.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
readlane_exec0.mir
[AMDGPU] Rename SIInsertSkips Pass
2021-03-20 11:48:04 +09:00
README
…
reassoc-scalar.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
reduce-build-vec-ext-to-ext-build-vec.ll
AMDGPU: Decompose all values to 32-bit pieces for calling conventions
2019-07-19 13:57:44 +00:00
reduce-load-width-alignment.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-06 10:32:44 -08:00
reduce-saveexec.mir
[AMDGPU] Add support for immediate operand for S_ENDPGM
2019-03-12 09:52:58 +00:00
reduce-store-width-alignment.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
reduction.ll
DAG: Combine extract_vector_elt of concat_vectors
2020-04-06 09:26:29 -04:00
reg-coalescer-sched-crash.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
regcoal-subrange-join-seg.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
regcoal-subrange-join.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
regcoalesce-cannot-join-failures.mir
[AMDGPU] Add support for immediate operand for S_ENDPGM
2019-03-12 09:52:58 +00:00
regcoalesce-dbg.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
[AMDGPU] Add support for immediate operand for S_ENDPGM
2019-03-12 09:52:58 +00:00
regcoalesce-prune.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
regcoalescing-remove-partial-redundancy-assert.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
register-count-comments.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
rel32.ll
[AMDGPU] Add some gfx1010 test coverage. NFC.
2021-03-18 14:00:07 +00:00
remove-short-exec-branches-gpr-idx-mode.mir
[AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole
2021-03-20 11:26:42 +09:00
remove-short-exec-branches-special-instructions.mir
[AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole
2021-03-20 11:26:42 +09:00
rename-disconnected-bug.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
rename-independent-subregs-mac-operands.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
rename-independent-subregs.mir
[AMDGPU] Add _e64 suffix to VOP3 Insts
2021-01-12 18:33:18 -05:00
reorder-stores.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
reqd-work-group-size.ll
[NewPM][AMDGPU] Port amdgpu-lower-kernel-attributes
2020-12-29 10:26:06 -08:00
reserve-vgpr-for-sgpr-spill.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
reserved-reg-in-clause.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
ret_jump.ll
[AMDGPU] Keep skip branch for ds instructions
2021-03-05 12:34:09 +01:00
ret.ll
AMDGPU/GlobalISel: Handle most function return types
2019-07-26 02:36:05 +00:00
return-with-successors.mir
AMDGPU: Implement getNoPreservedMask
2020-10-22 10:17:31 -04:00
returnaddress.ll
AMDGPU/GlobalISel: Select llvm.returnaddress
2020-08-04 17:14:38 -04:00
rewrite-out-arguments-address-space.ll
Use unary CreateShuffleVector if possible
2020-12-30 22:36:08 +09:00
rewrite-out-arguments.ll
Use unary CreateShuffleVector if possible
2020-12-30 22:36:08 +09:00
rotl.i64.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
rotl.ll
[AMDGPU] should expand ROTL i16 to shifts.
2020-09-17 17:34:33 +03:00
rotr.i64.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
rotr.ll
[AMDGPU] should expand ROTL i16 to shifts.
2020-09-17 17:34:33 +03:00
rsq.ll
AMDGPU: Remove v_rsq_f64 patterns
2021-01-21 10:51:36 -05:00
rv7x0_count3.ll
…
s_add_co_pseudo_lowering.mir
[AMDGPU] Add _e64 suffix to VOP3 Insts
2021-01-12 18:33:18 -05:00
s_addk_i32.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
s_code_end.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
s_movk_i32.ll
[AMDGPU] Switch scalarize global loads ON by default
2017-07-04 17:32:00 +00:00
s_mulk_i32.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
sad.ll
[EarlyCSE] Remove unnecessary operand swap.
2020-09-11 02:14:04 -04:00
saddo.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
saddsat.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
salu-to-valu.ll
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics
2020-07-17 11:02:13 +01:00
sampler-resource-id.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
scalar_to_vector_v2x16.ll
[AMDGPU] Restored selection of scalar_to_vector (v2x16)
2018-11-19 19:58:13 +00:00
scalar_to_vector.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
scalar-branch-missing-and-exec.ll
AMDGPU: Bring processors and features in sync with the spec
2018-02-16 21:26:25 +00:00
scalar-store-cache-flush.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
sched-assert-dead-def-subreg-use-other-subreg.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
sched-assert-onlydbg-value-empty-region.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
sched-crash-dbg-value.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
sched-handleMoveUp-subreg-def-across-subreg-def.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
sched-prefer-non-mfma.mir
[AMDGPU] Add _e64 suffix to VOP3 Insts
2021-01-12 18:33:18 -05:00
schedule-barrier-fpmode.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
schedule-barrier.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
schedule-fs-loop-nested-if.ll
AMDGPU: Remove llvm.AMDGPU.clamp intrinsic
2017-02-21 23:46:04 +00:00
schedule-fs-loop-nested.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
schedule-fs-loop.ll
AMDGPU: Remove llvm.AMDGPU.clamp intrinsic
2017-02-21 23:46:04 +00:00
schedule-global-loads.ll
[AMDGPU] Switch scalarize global loads ON by default
2017-07-04 17:32:00 +00:00
schedule-if-2.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
schedule-if.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
schedule-ilp.ll
AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
2017-11-20 14:35:53 +00:00
schedule-kernel-arg-loads.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
schedule-regpressure-limit2.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
schedule-regpressure-limit3.ll
[amdgpu] Enable use of AA during codegen.
2020-10-27 09:46:23 -04:00
schedule-regpressure-limit-clustering.ll
[AMDGPU] Fix not rescheduling without clustering
2020-08-07 11:15:58 -07:00
schedule-regpressure-limit.ll
[amdgpu] Enable use of AA during codegen.
2020-10-27 09:46:23 -04:00
schedule-regpressure.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
schedule-vs-if-nested-loop-failure.ll
[AMDGPU] Remove FeatureVGPRSpilling
2018-10-31 18:54:06 +00:00
schedule-vs-if-nested-loop.ll
…
schedule-xdl-resource.ll
[AMDGPU] Add XDL resource to scheduling model
2020-09-14 13:48:54 -07:00
scheduler-handle-move-bundle.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
scheduler-subrange-crash.ll
AMDGPU: Convert some tests to use new buffer intrinsics
2020-07-30 10:30:43 -04:00
scratch-buffer.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
scratch-simple.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
sdiv64.ll
[DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling
2021-03-19 16:02:31 +00:00
sdiv.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
sdivrem24.ll
[AMDGPU] Convert rcp to rcp_iflag
2018-06-27 15:33:33 +00:00
sdivrem64.r600.ll
AMDGPU: Enable integer division bypass
2020-02-19 17:50:19 -05:00
sdwa-gfx9.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
sdwa-op64-test.ll
AMDGPU: Match global saddr addressing mode
2020-08-17 15:28:14 -04:00
sdwa-ops.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
sdwa-peephole-instr-gfx10.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
sdwa-peephole-instr.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
sdwa-peephole.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
sdwa-preserve.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
sdwa-scalar-ops.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
sdwa-stack.mir
[AMDGPU] Inhibit SDWA if target instruction has FI
2020-08-13 11:34:28 -07:00
sdwa-vop2-64bit.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
select64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
select-constant-cttz.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
select-fabs-fneg-extract-legacy.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
select-fabs-fneg-extract.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
select-i1.ll
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
select-opt.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
select-undef.ll
Moved dag-combine-select-undef.ll into amdgpu. NFC.
2018-11-17 00:17:15 +00:00
select-vectors.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
select.f16.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
select.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
selectcc-cnd.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
selectcc-cnde-int.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
selectcc-icmp-select-float.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
selectcc-opt.ll
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
2020-08-03 10:22:25 -05:00
selectcc.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
sendmsg-m0-hazard.mir
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
set-dx10.ll
[FPEnv] Don't transform FSUB(-0,X)->FNEG(X) in SelectionDAGBuilder.
2020-08-03 10:22:25 -05:00
set-gpr-idx-peephole.mir
[AMDGPU] Remove set_gpr_idx instructions in conditional blocks
2021-04-30 22:15:45 +01:00
setcc64.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
setcc-equivalent.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
setcc-fneg-constant.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
setcc-limit-load-shrink.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
setcc-opt.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
setcc-sext.ll
[AMDGPU] Simplify setcc (sext from i1 b), -1|0, cc
2017-06-27 18:53:03 +00:00
setcc.ll
[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
2021-01-12 10:45:03 -08:00
seto.ll
AMDGPU: Remove some uses of llvm.SI.export in tests
2017-02-22 00:02:21 +00:00
setuo.ll
AMDGPU: Remove some uses of llvm.SI.export in tests
2017-02-22 00:02:21 +00:00
sext-divergence-driven-isel.ll
[AMDGPU] Enable SEXT divergence driven selection.
2020-03-17 17:30:11 +03:00
sext-eliminate.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
sext-in-reg-failure-r600.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
sext-in-reg.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
sgpr-control-flow.ll
[NFC][Test] Format the test with script update_llc_test_checks.py
2020-08-07 10:22:38 +00:00
sgpr-copy-duplicate-operand.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
sgpr-copy-local-cse.ll
[PeepholeOptimizer] Enhance the redundant COPY elimination.
2020-09-22 10:11:37 -04:00
sgpr-copy.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
sgpr-phys-copy.mir
[AMDGPU] Minimize number of s_mov generated by copyPhysReg
2020-10-15 22:35:02 +09:00
sgpr-spill-dead-frame-in-dbg-value.mir
[AMDGPU] Fix the dead frame indices during custom spill lowering.
2021-03-09 23:22:49 +05:30
sgpr-spill-partially-undef.mir
AMDGPU: Remove SGPRSpillVGPRDefinedSet hack
2020-12-16 21:33:35 -05:00
sgpr-spill-wrong-stack-id.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
sgpr-spill.mir
[AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks
2021-04-30 14:10:50 +01:00
sgprcopies.ll
AMDGPU : Fix common dominator of two incoming blocks terminates with uniform branch issue.
2017-04-12 23:51:47 +00:00
shader-addr64-nonuniform.ll
[AMDGPU] Support for v3i32/v3f32
2019-03-21 12:01:21 +00:00
shared-op-cycle.ll
…
shift-and-i64-ubfe.ll
[DAGCombine] Prune unnused nodes.
2019-03-29 17:35:56 +00:00
shift-and-i128-ubfe.ll
[AMDGPU] Fix dubious regexes with unescaped brackets. NFC.
2021-04-06 13:17:41 +01:00
shift-i64-opts.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
shift-i128.ll
Revert "[AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size"
2020-07-17 12:20:37 +05:30
shift-select.ll
[AMDGPU] fixed divergence driven shift operations selection
2020-01-31 20:49:56 +03:00
shl_add_constant.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
shl_add_ptr_csub.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
shl_add_ptr_global.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
shl_add_ptr.ll
[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions
2020-03-19 15:35:16 -04:00
shl_add.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
shl_or.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
shl-add-to-add-shl.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
shl.ll
[AMDGPU] Regenerate shift tests. NFCI.
2021-05-06 11:55:13 +01:00
shl.v2i16.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
shrink-add-sub-constant.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
shrink-carry.mir
[AMDGPU] Rename SIInsertSkips Pass
2021-03-20 11:48:04 +09:00
shrink-instructions-flags.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
shrink-instructions-illegal-fold.mir
[AMDGPU] Avoid an illegal operand in si-shrink-instructions
2021-01-28 08:49:21 +01:00
shrink-instructions-implicit-vcclo.mir
[AMDGPU] Preserve vcc_lo when shrinking V_CNDMASK
2020-08-27 10:22:50 +02:00
shrink-insts-scalar-bit-ops.mir
AMDGPU: Fix verifier error with undef source producing s_bitset*
2020-08-05 14:42:20 -04:00
shrink-vop3-carry-out.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
si-annotate-cf-kill.ll
[AMDGPU] Do not annotate an else branch if there is a kill
2021-03-12 11:52:08 +09:00
si-annotate-cf-noloop.ll
[AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree
2021-01-02 01:01:20 +03:00
si-annotate-cf-unreachable.ll
[AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32
2019-06-13 23:47:36 +00:00
si-annotate-cf.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
si-annotate-cfg-loop-assert.ll
[AMDGPU] Fix and extend vccz workarounds
2020-11-18 15:26:06 +00:00
si-annotatecfg-multiple-backedges.ll
AMDGPU: Fix extra type mangling on llvm.amdgcn.if.break
2020-02-03 07:02:05 -08:00
si-fix-sgpr-copies.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
si-i1-copies.mir
MachineSSAUpdater: insert IMPLICIT_DEF at top of basic block
2019-10-08 12:46:20 +00:00
si-instr-info-correct-implicit-operands.ll
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
si-lower-control-flow-kill.ll
AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsic
2018-04-24 21:37:57 +00:00
si-lower-control-flow-unreachable-block.ll
[AMDGPU] Keep skip branch for ds instructions
2021-03-05 12:34:09 +01:00
si-lower-control-flow.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
si-lower-i1-copies.mir
AMDGPU: Fix LCSSA phi lowering in SILowerI1Copies
2019-04-23 13:12:52 +00:00
si-lower-sgpr-spills.mir
[AMDGPU] Add test case on crashing of si-lower-sgpr-spills pass
2019-07-19 18:50:53 +00:00
si-scheduler.ll
[AMDGPU] Added -mcpu=tahiti to 3 tests. NFC.
2021-01-25 15:50:59 -08:00
si-sgpr-spill.ll
[AMDGPU] Added -mcpu=tahiti to 3 tests. NFC.
2021-01-25 15:50:59 -08:00
si-spill-cf.ll
AMDGPU: Convert tests away from llvm.SI.load.const
2019-01-17 22:47:26 +00:00
si-spill-sgpr-stack.ll
[AMDGPU] Save VGPR of whole wave when spilling
2021-04-12 11:01:38 +02:00
si-triv-disjoint-mem-access.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
si-vector-hang.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
sibling-call.ll
AMDGPU: Fix lit test
2021-05-05 18:41:18 -04:00
sign_extend.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
simple-indirect-call.ll
[AMDGPU] Remove error check for indirect calls and add missing queue-ptr
2021-04-20 00:35:17 +05:30
simplify-libcalls2.ll
[NewPM][AMDGPU] Port amdgpu-simplifylib/amdgpu-usenative
2020-12-28 10:38:51 -08:00
simplify-libcalls.ll
Reapply "[InferAttributes] Materialize all infered attributes for declaration"" and follow on patches.
2021-04-14 16:38:07 -07:00
simplifydemandedbits-recursion.ll
Use the return value of UpdateNodeOperands(); in some cases, UpdateNodeOperands() modifies the node in-place and using the return value isn’t strictly necessary. However, it does not necessarily modify the node, but may return a resultant node if it already exists in the DAG. See comments in UpdateNodeOperands(). In that case, the return value must be used to avoid such scenarios as an infinite loop (node is assumed to have been updated, so added back to the worklist, and re-processed; however, node hasn’t changed so it is once again passed to UpdateNodeOperands(), assumed modified, added back to worklist; cycle infinitely repeats).
2017-10-16 23:38:53 +00:00
sint_to_fp.f64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
sint_to_fp.i64.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
sint_to_fp.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
sitofp.f16.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
skip-branch-taildup-ret.mir
[AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole
2021-03-20 11:26:42 +09:00
skip-branch-trap.ll
[NFC] Removed unused prefixes in CodeGen/AMDGPU
2021-01-07 08:00:11 -08:00
skip-if-dead.ll
[AMDGPU] Use non-compressed exports in a test. NFC.
2021-03-23 11:18:12 +00:00
skip-promote-alloca-vector-users.ll
[AMDGPU] Skip promote-alloca for insertelement/insertvalue users
2021-04-30 08:37:26 +05:30
smed3.ll
[amdgpu] Update med3 combine to skip i64
2021-03-18 15:56:41 +00:00
smem-no-clause-coalesced.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
smem-war-hazard.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
sminmax.ll
AMDGPU: Move R600 test compatability hack
2020-02-10 10:02:06 -08:00
sminmax.v2i16.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
smrd_vmem_war.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
smrd-fold-offset.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
smrd-gfx10.ll
AMDGPU/GFX10: Support DLC bit in llvm.amdgcn.s.buffer.load intrinsic
2019-06-16 17:14:12 +00:00
smrd-vccz-bug.ll
[AMDGPU] Precommit some test updates for D68338 "Remove dubious logic in bidirectional list scheduler"
2020-02-25 14:51:42 +00:00
smrd.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
soft-clause-dbg-value.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
soft-clause-exceeds-register-budget.ll
[AMDGPU] Switch AnnotateUniformValues to MemorySSA
2021-05-05 18:34:41 -07:00
sopk-compares.ll
AMDGPU: Explicitly define a triple for some tests
2019-06-17 19:25:57 +00:00
speculative-execution-freecasts.ll
SpeculativeExecution: fixed ingoring free execution
2020-02-20 14:45:02 +03:00
spill192.mir
AMDGPU: Remove SGPRSpillVGPRDefinedSet hack
2020-12-16 21:33:35 -05:00
spill_more_than_wavesize_csr_sgprs.ll
[AMDGPU] Use pseudo instructions for readlane/writelane
2020-10-29 16:00:53 +00:00
spill-agpr-partially-undef.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
spill-agpr.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
spill-agpr.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
spill-alloc-sgpr-init-bug.ll
AMDGPU: Fix register name format in tests
2018-03-27 18:39:42 +00:00
spill-before-exec.mir
[AMDGPU] Remove weird target triples from tests. NFC.
2021-03-19 16:48:32 +00:00
spill-cfg-position.ll
AMDGPU: Assume xnack is enabled by default
2019-05-16 14:48:34 +00:00
spill-csr-frame-ptr-reg-copy.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
spill-empty-live-interval.mir
[AMDGPU] Remove scratch rsrc from spill pseudos
2020-11-12 15:23:37 -08:00
spill-m0.ll
[AMDGPU] Save VGPR of whole wave when spilling
2021-04-12 11:01:38 +02:00
spill-offset-calculation.ll
[AMDGPU] Fix typo in regular expression checks. NFC.
2021-04-06 12:29:48 +01:00
spill-reg-tuple-super-reg-use.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
spill-scavenge-offset.ll
[AMDGPU] Mark scavenged SGPR as used
2021-04-14 14:55:01 +02:00
spill-sgpr-csr-live-ins.mir
AMDGPU: Fix verifier error with argument passed in CSR SGPR
2021-02-09 13:49:44 -05:00
spill-sgpr-stack-no-sgpr.ll
[AMDGPU] Save VGPR of whole wave when spilling
2021-04-12 11:01:38 +02:00
spill-special-sgpr.mir
[AMDGPU] Kill temporary register after restoring
2021-04-12 14:20:03 +02:00
spill-vgpr-to-agpr.ll
AMDGPU: Use kill instruction to hint soft clause live ranges
2021-02-26 18:26:40 -05:00
spill-wide-sgpr.ll
[NFC][AMDGPU] Clean up some lit test prefixes
2020-11-11 17:12:37 +00:00
split-arg-dbg-value.ll
[MCAsmInfo] Support UsesCFIForDebug for targets with no exception handling
2021-05-06 04:53:45 +05:30
split-scalar-i64-add.ll
CodeGen: Make computeRegisterLiveness consider successors
2018-08-30 07:17:51 +00:00
split-smrd.ll
AMDGPU: Drop remnants of byval support for shaders
2019-07-12 20:12:17 +00:00
split-vector-memoperand-offsets.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
splitkit-copy-bundle.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
splitkit-copy-live-lanes.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
splitkit-getsubrangeformask.ll
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
splitkit-nolivesubranges.mir
[VirtRegRewriter] Insert missing killed flags when tracking subregister liveness
2021-03-03 12:02:04 -05:00
splitkit.mir
[VirtRegRewriter] Insert missing killed flags when tracking subregister liveness
2021-03-03 12:02:04 -05:00
sra.ll
[AMDGPU] Regenerate shift tests. NFCI.
2021-05-06 11:55:13 +01:00
sram-ecc-default.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
sramecc-subtarget-feature-any.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
sramecc-subtarget-feature-disabled.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
sramecc-subtarget-feature-enabled.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
srem64.ll
[AMDGPU] Remove MachineDCE after SIFoldOperands
2021-04-19 12:08:02 +01:00
srem-seteq-illegal-types.ll
Support {S,U}REMEqFold before legalization
2021-04-01 01:35:41 +03:00
srem.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
srl.ll
[AMDGPU] Regenerate shift tests. NFCI.
2021-05-06 11:55:13 +01:00
sroa-before-unroll.ll
[AMDGPU][NewPM] Port amdgpu-promote-alloca(-to-vector)
2020-12-28 17:52:31 -08:00
SRSRC-GIT-clobber-check.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
ssubo.ll
[CodeGen] Handle vector UADDO, SADDO, USUBO, SSUBO
2019-02-07 21:02:22 +00:00
ssubsat.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
stack-pointer-offset-relative-frameindex.ll
[AMDGPU] Don't check for VMEM hazards on GFX10
2021-03-04 21:44:56 +00:00
stack-realign-kernel.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
stack-realign.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
stack-size-overflow.ll
AMDGPU: Lower the threshold reported for maximum stack size exceeded
2020-10-21 12:06:27 -04:00
stack-slot-color-sgpr-vgpr-spills.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
stale-livevar-in-twoaddr-pass.mir
[AMDGPU] Add _e64 suffix to VOP3 Insts
2021-01-12 18:33:18 -05:00
store_typed.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
store-barrier.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
store-clobbers-load.ll
AMDGPU: Annotate amdgpu.noclobber for global loads only
2021-01-05 14:47:19 -08:00
store-global.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
store-hi16.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
store-local.96.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
store-local.128.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
store-local.ll
[AMDGPU] Set DS alignment requirements to be more strict
2020-09-18 15:26:24 +02:00
store-private.ll
AMDGPU: Stop trying to extend arguments for clover
2018-07-28 12:34:25 +00:00
store-v3i64.ll
AMDGPU: Use 128-bit DS operations by default
2020-04-02 17:17:47 -04:00
store-vector-ptrs.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
store-weird-sizes.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
stress-calls.ll
Reapply "AMDGPU: Force inlining if LDS global address is used"
2018-07-10 14:03:41 +00:00
strict_fadd.f16.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
strict_fadd.f32.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
strict_fadd.f64.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
strict_fma.f16.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
strict_fma.f32.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
strict_fma.f64.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
strict_fmul.f16.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
strict_fmul.f32.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
strict_fmul.f64.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
strict_fsub.f16.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
strict_fsub.f32.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
strict_fsub.f64.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
structurize1.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
structurize.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
sub_i1.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
sub-zext-cc-zext-cc.ll
[AMDGPU] Extend macro fusion for ADDC and SUBB to SUBBREV
2020-03-11 17:59:21 +00:00
sub.i16.ll
[AMDGPU][MC] Corrected decoding of 16-bit literals
2020-07-22 17:20:43 +03:00
sub.ll
AMDGPU: Select VOP3 form of sub
2019-05-03 15:37:07 +00:00
sub.v2i16.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
subreg_interference.mir
[VirtRegRewriter] Insert missing killed flags when tracking subregister liveness
2021-03-03 12:02:04 -05:00
subreg-coalescer-crash.ll
AMDGPU: Convert test cases to the dimension-aware intrinsics
2018-06-21 13:37:19 +00:00
subreg-coalescer-undef-use.ll
Resubmit: [AMDGPU] Invert the handling of skip insertion.
2020-01-22 13:18:32 +09:00
subreg-eliminate-dead.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
subreg-intervals.mir
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
subreg-split-live-in-error.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
subreg-undef-def-with-other-subreg-defs.mir
[AMDGPU] Define AGPR subregs
2020-04-28 15:30:43 -07:00
subvector-test.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
swdev282079.ll
AMDGPU: Fix assert on inline asm on gfx90a
2021-04-23 09:00:25 -04:00
swdev282079.mir
AMDGPU: Fix assert on inline asm on gfx90a
2021-04-23 09:00:25 -04:00
switch-default-block-unreachable.ll
[AMDGPU] Move LowerSwitch pass to CodeGenPrepare.
2020-07-11 16:33:38 +05:30
switch-unreachable.ll
[AMDGPU] add generated checks for some LIT tests
2020-03-03 11:47:05 +05:30
swizzle-export.ll
…
syncscopes.ll
[AMDGPU] Rename SIInsertSkips Pass
2021-03-20 11:48:04 +09:00
tail-call-amdgpu-gfx.ll
AMDGPU: Allow tail calls for amdgpu_gfx functions
2021-03-22 10:55:19 -04:00
tail-call-cgp.ll
AMDGPU: Start adding tail call support
2017-08-11 20:42:08 +00:00
tail-dup-bundle.mir
Process BUNDLE in tail duplication
2020-01-15 15:46:57 -08:00
tail-duplication-convergent.ll
AMDGPU: Add intrinsics for DS GWS semaphore instructions
2019-06-20 21:11:42 +00:00
target-cpu.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
tex-clause-antidep.ll
…
texture-input-merge.ll
…
tgsplit.ll
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
tid-code-object-v2-backwards-compatibility.ll
AMDGPU: Add gfx90c support to code object v2 for backwards compatibility
2021-04-08 16:42:43 -04:00
tid-mul-func-xnack-all-any.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-all-not-supported.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-all-off.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-all-on.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-off-1.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-off-2.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-on-1.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-any-on-2.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-mul-func-xnack-invalid-any-off-on.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-one-func-xnack-any.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-one-func-xnack-not-supported.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-one-func-xnack-off.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
tid-one-func-xnack-on.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
token-factor-inline-limit-test.ll
[AMDGPU] Don't cluster stores
2020-09-14 13:40:17 +01:00
transform-block-with-return-to-epilog.ll
[AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole
2021-03-20 11:26:42 +09:00
trap-abis.ll
AMDGPU: Add target id and code object v4 support
2021-03-24 11:54:05 -04:00
trap.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
trunc-bitcast-vector.ll
[AMDGPU] combine extractelement into several selects
2018-11-13 21:18:21 +00:00
trunc-cmp-constant.ll
[AMDGPU] Fix CHECK lines
2020-04-03 10:07:21 +01:00
trunc-combine.ll
[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24
2021-02-23 15:39:19 +00:00
trunc-store-f64-to-f16.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
trunc-store-i1.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-07 09:48:14 -08:00
trunc-store-i64.ll
AMDGPU: Select global saddr mode from SGPR pointer
2020-11-16 11:51:06 -05:00
trunc-store-vec-i16-to-i8.ll
[AMDGPU] Expand vector trunc stores from i16 to i8
2020-04-07 21:47:45 -07:00
trunc-store.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
trunc-vector-store-assertion-failure.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
trunc.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
tti-unroll-prefs.ll
AMDGPU: Remove -mcpu=SI
2017-08-07 18:30:35 +00:00
twoaddr-fma-f64.mir
AMDGPU: Add even aligned VGPR/AGPR register classes
2021-02-24 14:49:37 -05:00
twoaddr-fma.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
twoaddr-mad.mir
[AMDGPU] Add _e64 suffix to VOP3 Insts
2021-01-12 18:33:18 -05:00
uaddo.ll
AMDGPU: Fix capitalized register names in asm constraints
2019-06-14 21:16:06 +00:00
uaddsat.ll
[DAG] PromoteIntRes_ADDSUBSHLSAT - promote ISD::UADDSAT as clamped add
2021-02-16 17:37:44 +00:00
udiv64.ll
[AMDGPU] Remove MachineDCE after SIFoldOperands
2021-04-19 12:08:02 +01:00
udiv.ll
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
udivrem24.ll
[llvm] Fix missing FileCheck directive colons
2020-04-06 09:59:08 -06:00
udivrem64.r600.ll
AMDGPU: Cleanup and generate 64-bit div tests
2020-01-20 17:19:39 -05:00
udivrem.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
uint_to_fp.f64.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
uint_to_fp.i64.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-07 09:48:14 -08:00
uint_to_fp.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
uitofp.f16.ll
AMDGPU: Fix some incorrect FUNC-LABEL checks
2020-02-26 09:43:13 +00:00
umed3.ll
Reapply [ValueTracking] Support min/max selects in computeConstantRange()
2019-04-07 17:22:16 +00:00
unaligned-load-store.ll
[AMDGPU] Support unaligned flat scratch in TLI
2020-12-22 16:12:31 -08:00
unallocatable-bundle-regression.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
undef-subreg-use-after-coalesce.mir
RegisterCoalescer: Fix not setting undef on coalesced subregister uses
2021-02-03 13:54:43 -05:00
undefined-physreg-sgpr-spill.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
undefined-subreg-liverange.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
unexpected-reg-unit-state.mir
[AMDGPU] Remove scratch rsrc from spill pseudos
2020-11-12 15:23:37 -08:00
unhandled-loop-condition-assertion.ll
Revert "[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC"
2020-05-22 05:36:15 -06:00
uniform-branch-intrinsic-cond.ll
AMDGPU: Update tests to use modern buffer intrinsics
2020-01-16 13:49:43 -05:00
uniform-cfg.ll
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
uniform-crash.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
uniform-loop-inside-nonuniform.ll
[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.
2020-04-06 09:05:58 -04:00
uniform-work-group-attribute-missing.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
uniform-work-group-nested-function-calls.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
uniform-work-group-prevent-attribute-propagation.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
uniform-work-group-propagate-attribute.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
uniform-work-group-recursion-test.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
uniform-work-group-test.ll
AMDGPU: Directly annotate functions if they have calls
2020-03-12 19:10:59 -04:00
unify-metadata.ll
[NewPM][AMDGPU] Port amdgpu-unify-metadata
2021-01-04 11:57:46 -08:00
unigine-liveness-crash.ll
[AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree
2021-01-02 01:01:20 +03:00
unknown-processor.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
unpack-half.ll
[SelectionDAG] Fixed f16-from-vector promotion problem
2018-01-09 21:36:25 +00:00
unroll.ll
[AMDGPU][CostModel] Refine cost model for control-flow instructions.
2021-04-10 09:20:24 +03:00
unstructured-cfg-def-use-issue.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
unsupported-calls.ll
[AMDGPU] Remove error check for indirect calls and add missing queue-ptr
2021-04-20 00:35:17 +05:30
unsupported-cc.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
unsupported-image-a16.ll
[AMDGPU] Implement mir parseCustomPseudoSourceValue
2021-01-22 11:24:08 +01:00
unsupported-image-g16.ll
[AMDGPU] Implement mir parseCustomPseudoSourceValue
2021-01-22 11:24:08 +01:00
update-phi.ll
[AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}DomTree
2021-01-02 01:01:20 +03:00
urem64.ll
[AMDGPU] Remove MachineDCE after SIFoldOperands
2021-04-19 12:08:02 +01:00
urem-seteq-illegal-types.ll
Support {S,U}REMEqFold before legalization
2021-04-01 01:35:41 +03:00
urem.ll
[AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32
2019-05-06 22:27:05 +00:00
use-sgpr-multiple-times.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
usubo.ll
AMDGPU: Fix capitalized register names in asm constraints
2019-06-14 21:16:06 +00:00
usubsat.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
v1i64-kernel-arg.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
v1024.ll
[AMDGPU] Change register type for v32 vectors
2019-07-16 20:06:00 +00:00
v_cndmask.ll
[AMDGPU] Tidy up a FIXME fixed by D34973
2021-02-18 14:28:27 +00:00
v_cvt_pk_u8_f32.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
v_mac_f16.ll
[FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when subnormals are flushed
2021-01-04 14:44:10 -06:00
v_mac.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
v_madak_f16.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
v_mov_b64_expansion.mir
[AMDGPU] gfx90a support
2021-02-17 16:01:32 -08:00
v_swap_b32.mir
[AMDGPU] Fix v_swap_b32 formation on physical registers
2021-04-29 20:53:40 +01:00
valu-i1.ll
[AMDGPU] Fix typo in regular expression checks. NFC.
2021-04-06 12:29:48 +01:00
vccz-corrupt-bug-workaround.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
vcmpx-exec-war-hazard.mir
[AMDGPU] Move kill lowering to WQM pass and add live mask tracking
2021-02-11 20:31:29 +09:00
vcmpx-permlane-hazard.mir
[AMDGPU] Move kill lowering to WQM pass and add live mask tracking
2021-02-11 20:31:29 +09:00
vector_shuffle.packed.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
vector-alloca-addrspacecast.ll
AMDGPU/SI: Don't promote alloca to vector for AddrSpaceCast instruction.
2018-05-11 22:17:57 +00:00
vector-alloca-atomic.ll
AMDGPU/SI: Don't promote alloca to vector for atomic load/store
2018-05-17 21:49:44 +00:00
vector-alloca-bitcast.ll
[InstCombine] use poison as placeholder for undemanded elems
2020-12-28 08:58:15 +09:00
vector-alloca-limits.ll
[AMDGPU] Limit promote alloca to vector with VGPR budget
2020-07-01 15:57:24 -07:00
vector-alloca.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-07 09:48:14 -08:00
vector-extract-insert.ll
[AMDGPU] Add volatile support to SIMemoryLegalizer
2021-01-09 00:52:33 +00:00
vector-legalizer-divergence.ll
[CodeGen] Always update divergence in SelectionDAG::UpdateNodeOperands
2018-06-04 20:19:45 +00:00
vectorize-buffer-fat-pointer.ll
[AMDGPU] Add an experimental buffer fat pointer address space.
2019-03-18 14:44:28 +00:00
vectorize-global-local.ll
[AMDGPU] Switch scalarize global loads ON by default
2017-07-04 17:32:00 +00:00
vectorize-loads.ll
[amdgpu] Add the late codegen preparation pass.
2020-10-27 14:07:59 -04:00
verify-constant-bus-violations.mir
[AMDGPU] Consider all SGPR uses as unique in constant bus verify
2020-09-24 10:52:40 +09:00
verify-duplicate-literal.mir
[AMDGPU] Allow multiple uses of the same literal
2021-04-20 16:44:01 +01:00
verify-gfx90a-aligned-vgprs.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
verify-sop.mir
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
vertex-fetch-encoding.ll
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
vgpr-descriptor-waterfall-loop-idom-update.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
vgpr-remat.mir
[AMDGPU] Fix isReallyTriviallyReMaterializable for V_MOV_*
2021-03-10 16:18:12 +00:00
vgpr-spill-dead-frame-in-dbg-value.mir
[AMDGPU] Fix the dead frame indices during custom spill lowering.
2021-03-09 23:22:49 +05:30
vgpr-spill-emergency-stack-slot-compute.ll
AMDGPU: Update AMDHSA code object version handling
2020-10-14 13:04:27 -04:00
vgpr-spill-emergency-stack-slot.ll
[CodeGen] Ensure callers of CreateStackTemporary use sensible alignments
2020-06-09 08:10:17 +01:00
vgpr-spill.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
vgpr-tuple-allocation.ll
[AMDGPU] Set implicit arg attributes for indirect calls
2021-04-13 13:15:13 +00:00
vi-removed-intrinsics.ll
Reapply "Adapt gcov to changes in CFE."
2018-12-06 18:44:48 +00:00
virtregrewrite-undef-identity-copy.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
visit-physreg-vgpr-imm-folding-bug.ll
Revert "[AMDGPU] Insert waitcnt after returning from call"
2020-09-23 17:16:39 +02:00
vmem-to-salu-hazard.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
vmem-vcc-hazard.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
vop-shrink-frame-index.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
vop-shrink-non-ssa.mir
AMDGPU: Rename add/sub with carry out instructions
2020-07-16 13:16:30 -04:00
vop-shrink.ll
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
2017-11-20 18:24:21 +00:00
vselect64.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
vselect.ll
Fix 64-bit copy to SCC
2020-08-09 20:50:30 +02:00
vtx-fetch-branch.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
vtx-schedule.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
wait.ll
[AMDGPU] Order pos exports before param exports
2020-05-12 23:02:23 +09:00
waitcnt-agpr.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
waitcnt-back-edge-loop.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
waitcnt-debug.mir
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
waitcnt-flat.ll
[AMDGPU] Switch to the new addr space mapping by default
2018-02-02 16:07:16 +00:00
waitcnt-loop-irreducible.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
waitcnt-loop-single-basic-block.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
waitcnt-looptest.ll
[AMDGPU] Optimize waitcnt insertion for flat memory operations
2020-10-20 22:55:12 +00:00
waitcnt-meta-instructions.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
waitcnt-no-redundant.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
waitcnt-overflow.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
waitcnt-permute.mir
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
waitcnt-preexisting-vscnt.mir
[AMDGPU] Revise handling of preexisting waitcnt
2021-05-05 17:21:33 -07:00
waitcnt-preexisting.mir
[AMDGPU] Move insertion of function entry waitcnt later
2021-05-05 17:58:38 -07:00
waitcnt-skip-meta.mir
[AMDGPU] Skip CFIInstructions in SIInsertWaitcnts
2020-06-17 12:41:03 -04:00
waitcnt-vmem-waw.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
waitcnt-vscnt.ll
[AMDGPU] Optimize waitcnt insertion for flat memory operations
2020-10-20 22:55:12 +00:00
waitcnt-vscnt.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
waitcnt.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
wave32.ll
[AMDGPU] Fix typo in regular expression checks. NFC.
2021-04-06 12:29:48 +01:00
wave_dispatch_regs.ll
[AMDGPU] Emit new pal metadata by default
2020-10-26 10:16:17 +01:00
widen_extending_scalar_loads.ll
Make IRBuilder automatically set alignment on load/store/alloca.
2020-04-13 13:43:14 -07:00
widen-smrd-loads.ll
[DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE (REAPPLIED).
2021-01-21 13:01:34 +00:00
widen-vselect-and-mask.ll
DAG: Fix creating select with wrong condition type
2017-10-25 07:14:07 +00:00
wqm.ll
[AMDGPU] Fix shortfalls in WQM marking
2021-03-15 21:44:15 +09:00
wqm.mir
[AMDGPU] Use single cache policy operand
2021-03-15 13:00:59 -07:00
write_register.ll
AMDGPU: Split test function
2020-01-12 22:44:51 -05:00
write-register-vgpr-into-sgpr.ll
[AMDGPU] Eliminate no effect instructions before s_endpgm
2017-08-16 04:43:49 +00:00
wrong-transalu-pos-fix.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
wwm-reserved-spill.ll
[AMDGPU] Fix autogenerated wwm-reserved-spill.ll
2021-04-26 19:09:09 +02:00
wwm-reserved.ll
[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm
2021-03-03 09:33:57 +01:00
xfail.r600.bitcast.ll
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
2017-03-21 21:39:51 +00:00
xnack-subtarget-feature-any.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
xnack-subtarget-feature-disabled.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
xnack-subtarget-feature-enabled.ll
[AMDGPU] Update subtarget features for new target ID support
2021-01-26 11:25:51 -08:00
xnor.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-07 09:48:14 -08:00
xor3-i1-const.ll
[AMDGPU] Fixed handling of imemdiate i1 literals
2019-05-14 16:18:00 +00:00
xor3.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
xor_add.ll
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
2020-12-02 10:11:42 +00:00
xor.ll
AMDGPU: Add pass to lower kernel arguments to loads
2018-06-26 19:10:00 +00:00
zero_extend.ll
[NFC] Removed unused prefixes from CodeGen/AMDGPU
2021-01-07 09:48:14 -08:00
zext-i64-bit-operand.ll
AMDGPU: Allow SIShrinkInstructions to work in non-SSA
2017-07-10 19:53:57 +00:00
zext-lid.ll
[AMDGPU] Packed thread ids in function call ABI
2019-06-28 01:52:13 +00:00

README 

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.
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