Matt Arsenault 96b9e12990 AMDGPU: Add VOP3P instruction format ... Add a few non-VOP3P but instructions related to packed. Includes hack with dummy operands for the benefit of the assembler llvm-svn: 296368		2017-02-27 18:49:11 +00:00
..
AArch64	[AArch64] Add Cavium ThunderX support	2017-02-17 18:34:24 +00:00
AMDGPU	AMDGPU: Add VOP3P instruction format	2017-02-27 18:49:11 +00:00
ARM	[ARM] LSL #0 is an alias of MOV	2017-02-27 14:40:51 +00:00
AsmParser	Move test input to directory called Inputs.	2017-01-06 10:22:15 +00:00
AVR	[AVR] Add all of the machine code test suite	2016-11-09 23:46:25 +00:00
COFF	MC/COFF: Do not emit forward associative section referenceds.	2017-02-17 17:32:54 +00:00
Disassembler	AMDGPU: Fix disassembly of aperture registers	2017-02-18 18:41:41 +00:00
ELF	Disallow redefinition of section symbols.	2017-02-24 21:44:58 +00:00
Hexagon	[Hexagon] Introduce Hexagon V62	2017-02-10 23:46:45 +00:00
Lanai	[lanai] Add more tests for assembly of conditional ALU ops	2016-07-11 17:58:16 +00:00
MachO	MCMacho: Allow __thread_ptr section after dwarf sections	2017-02-01 01:31:36 +00:00
Markup
Mips	[mips] Handle 64 bit immediate in and/or/xor pseudo instructions on mips64	2017-02-24 14:34:32 +00:00
PowerPC	[PowerPC][Altivec] Add vnot extended mnemonic	2017-02-07 18:57:29 +00:00
Sparc	Don't pass a Reloc::Model to MC.	2016-05-18 11:58:50 +00:00
SystemZ	[SystemZ] Support remaining atomic instructions	2016-12-02 18:24:16 +00:00
WebAssembly	[WebAssembly] Implement the wasm binary container header.	2017-02-22 18:50:20 +00:00
X86	[X86] Clzero intrinsic and its addition under znver1	2017-02-09 04:27:34 +00:00