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5efe040582
Initialize all AArch64-specific passes in the TargetMachine so they can be run by llc. This can lead to conflicts in opt with some command line options that share the same name as the pass, so I took this opportunity to do some cleanups: * rename all relevant command line options from "aarch64-blah" to "aarch64-enable-blah" and update the tests accordingly * run clang-format on their declarations * move all these declarations to a common place (the TargetMachine) as opposed to having them scattered around (AArch64BranchRelaxation and AArch64AddressTypePromotion were the only offenders) llvm-svn: 277322
32 lines
1.1 KiB
LLVM
32 lines
1.1 KiB
LLVM
; RUN: llc %s -o - -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
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; Check that ANDS (tst) is not merged with ADD when the immediate
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; is not 0.
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; <rdar://problem/16693089>
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-ios"
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; CHECK-LABEL: tst1:
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; CHECK: add [[REG:w[0-9]+]], w{{[0-9]+}}, #1
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; CHECK: tst [[REG]], #0x1
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define void @tst1(i1 %tst, i32 %true) {
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entry:
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br i1 %tst, label %for.end, label %for.body
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for.body: ; preds = %for.body, %entry
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%result.09 = phi i32 [ %add2.result.0, %for.body ], [ 1, %entry ]
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%i.08 = phi i32 [ %inc, %for.body ], [ 2, %entry ]
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%and = and i32 %i.08, 1
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%cmp1 = icmp eq i32 %and, 0
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%add2.result.0 = select i1 %cmp1, i32 %true, i32 %result.09
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%inc = add nsw i32 %i.08, 1
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%cmp = icmp slt i32 %i.08, %true
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br i1 %cmp, label %for.body, label %for.cond.for.end_crit_edge
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for.cond.for.end_crit_edge: ; preds = %for.body
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%add2.result.0.lcssa = phi i32 [ %add2.result.0, %for.body ]
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br label %for.end
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for.end: ; preds = %for.cond.for.end_crit_edge, %entry
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ret void
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}
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