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b3ee777d21
Providing that the load is known to be 4 byte aligned, we can optimise a ldr(adr address) to just ldr address. Differential Revision: https://reviews.llvm.org/D51030 llvm-svn: 341058
53 lines
1.1 KiB
LLVM
53 lines
1.1 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-eabi -code-model=tiny < %s | FileCheck %s
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@var8 = global i8 0
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@var16 = global i16 0
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@var32 = global i32 0
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@var64 = global i64 0
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define i8* @global_addr() {
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; CHECK-LABEL: global_addr:
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ret i8* @var8
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; The adr calculation should end up returned directly in x0.
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; CHECK: adr x0, var8
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; CHECK-NEXT: ret
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}
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define i8 @global_i8() {
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; CHECK-LABEL: global_i8:
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%val = load i8, i8* @var8
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ret i8 %val
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; CHECK: adr x[[ADDR_REG:[0-9]+]], var8
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; CHECK: ldrb w0, [x[[ADDR_REG]]]
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}
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define i16 @global_i16() {
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; CHECK-LABEL: global_i16:
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%val = load i16, i16* @var16
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ret i16 %val
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; CHECK: adr x[[ADDR_REG:[0-9]+]], var16
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; CHECK: ldrh w0, [x[[ADDR_REG]]]
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}
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define i32 @global_i32() {
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; CHECK-LABEL: global_i32:
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%val = load i32, i32* @var32
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ret i32 %val
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; CHECK: ldr w0, var32
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}
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define i64 @global_i64() {
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; CHECK-LABEL: global_i64:
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%val = load i64, i64* @var64
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ret i64 %val
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; CHECK: ldr x0, var64
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}
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define <2 x i64> @constpool() {
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; CHECK-LABEL: constpool:
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ret <2 x i64> <i64 123456789, i64 987654321100>
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; CHECK: adr x[[ADDR_REG:[0-9]+]], {{.LCPI[0-9]+_[0-9]+}}
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; CHECK: ldr q0, [x[[ADDR_REG]]]
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}
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