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a5f9319c39
Following the ARM-neon backend, define isExtractSubvectorCheap to return true when extracting low and high part of a neon register. The patch disables a test in llvm/test/CodeGen/AArch64/arm64-ext.ll This testcase is fragile in the sense that it requires a BUILD_VECTOR to "survive" all DAG transforms until ISelLowering. The testcase is supposed to check that AArch64TargetLowering::ReconstructShuffle() works, and for that we need a BUILD_VECTOR in ISelLowering. As we now transform the BUILD_VECTOR earlier into an VEXT + vector_shuffle, we don't have the BUILD_VECTOR pattern when we get to ISelLowering. As there is no way to disable the combiner to only exercise the code in ISelLowering, the patch disables the testcase. Differential revision: https://reviews.llvm.org/D43973 llvm-svn: 326811
164 lines
4.9 KiB
LLVM
164 lines
4.9 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -asm-verbose=false < %s | FileCheck %s
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define float @test_dup_sv2S(<2 x float> %v) #0 {
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; CHECK-LABEL: test_dup_sv2S:
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; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1]
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; CHECK-NEXT: ret
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%tmp1 = extractelement <2 x float> %v, i32 1
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ret float %tmp1
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}
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define float @test_dup_sv2S_0(<2 x float> %v) #0 {
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; CHECK-LABEL: test_dup_sv2S_0:
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; CHECK-NOT: dup {{[vsd][0-9]+}}
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; CHECK-NOT: ins {{[vsd][0-9]+}}
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; CHECK-NEXT: ret
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%tmp1 = extractelement <2 x float> %v, i32 0
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ret float %tmp1
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}
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define float @test_dup_sv4S(<4 x float> %v) #0 {
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; CHECK-LABEL: test_dup_sv4S:
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; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1]
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; CHECK-NEXT: ret
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%tmp1 = extractelement <4 x float> %v, i32 1
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ret float %tmp1
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}
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define float @test_dup_sv4S_0(<4 x float> %v) #0 {
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; CHECK-LABEL: test_dup_sv4S_0:
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; CHECK-NOT: dup {{[vsd][0-9]+}}
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; CHECK-NOT: ins {{[vsd][0-9]+}}
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; CHECK-NEXT: ret
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%tmp1 = extractelement <4 x float> %v, i32 0
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ret float %tmp1
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}
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define double @test_dup_dvD(<1 x double> %v) #0 {
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; CHECK-LABEL: test_dup_dvD:
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; CHECK-NOT: dup {{[vsd][0-9]+}}
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; CHECK-NOT: ins {{[vsd][0-9]+}}
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; CHECK-NEXT: ret
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%tmp1 = extractelement <1 x double> %v, i32 0
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ret double %tmp1
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}
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define double @test_dup_dv2D(<2 x double> %v) #0 {
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; CHECK-LABEL: test_dup_dv2D:
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; CHECK-NEXT: mov d{{[0-9]+}}, {{v[0-9]+}}.d[1]
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; CHECK-NEXT: ret
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%tmp1 = extractelement <2 x double> %v, i32 1
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ret double %tmp1
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}
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define double @test_dup_dv2D_0(<2 x double> %v) #0 {
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; CHECK-LABEL: test_dup_dv2D_0:
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; CHECK-NOT: dup {{[vsd][0-9]+}}
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; CHECK-NOT: ins {{[vsd][0-9]+}}
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; CHECK-NEXT: ret
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%tmp1 = extractelement <2 x double> %v, i32 0
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ret double %tmp1
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}
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define half @test_dup_hv8H(<8 x half> %v) #0 {
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; CHECK-LABEL: test_dup_hv8H:
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; CHECK-NEXT: mov h{{[0-9]+}}, {{v[0-9]+}}.h[1]
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; CHECK-NEXT: ret
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%tmp1 = extractelement <8 x half> %v, i32 1
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ret half %tmp1
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}
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define half @test_dup_hv8H_0(<8 x half> %v) #0 {
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; CHECK-LABEL: test_dup_hv8H_0:
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; CHECK-NOT: dup {{[vsdh][0-9]+}}
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; CHECK-NOT: ins {{[vsdh][0-9]+}}
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; CHECK-NEXT: ret
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%tmp1 = extractelement <8 x half> %v, i32 0
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ret half %tmp1
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}
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define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) #0 {
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; CHECK-LABEL: test_vector_dup_bv16B:
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; CHECK-NEXT: dup v0.8b, v0.b[14]
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; CHECK-NEXT: ret
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%shuffle.i = shufflevector <16 x i8> %v1, <16 x i8> undef, <1 x i32> <i32 14>
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ret <1 x i8> %shuffle.i
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}
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define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) #0 {
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; CHECK-LABEL: test_vector_dup_bv8B:
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; CHECK-NEXT: dup v0.8b, v0.b[7]
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; CHECK-NEXT: ret
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%shuffle.i = shufflevector <8 x i8> %v1, <8 x i8> undef, <1 x i32> <i32 7>
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ret <1 x i8> %shuffle.i
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}
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define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) #0 {
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; CHECK-LABEL: test_vector_dup_hv8H:
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; CHECK-NEXT: dup v0.4h, v0.h[7]
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; CHECK-NEXT: ret
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%shuffle.i = shufflevector <8 x i16> %v1, <8 x i16> undef, <1 x i32> <i32 7>
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ret <1 x i16> %shuffle.i
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}
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define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) #0 {
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; CHECK-LABEL: test_vector_dup_hv4H:
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; CHECK-NEXT: dup v0.4h, v0.h[3]
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; CHECK-NEXT: ret
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%shuffle.i = shufflevector <4 x i16> %v1, <4 x i16> undef, <1 x i32> <i32 3>
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ret <1 x i16> %shuffle.i
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}
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define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) #0 {
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; CHECK-LABEL: test_vector_dup_sv4S:
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; CHECK-NEXT: dup v0.2s, v0.s[3]
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; CHECK-NEXT: ret
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%shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32> <i32 3>
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ret <1 x i32> %shuffle
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}
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define <1 x i32> @test_vector_dup_sv2S(<2 x i32> %v1) #0 {
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; CHECK-LABEL: test_vector_dup_sv2S:
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; CHECK-NEXT: dup v0.2s, v0.s[1]
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; CHECK-NEXT: ret
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%shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <1 x i32> <i32 1>
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ret <1 x i32> %shuffle
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}
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define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) #0 {
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; CHECK-LABEL: test_vector_dup_dv2D:
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; CHECK-NEXT: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #8
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; CHECK-NEXT: ret
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%shuffle.i = shufflevector <2 x i64> %v1, <2 x i64> undef, <1 x i32> <i32 1>
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ret <1 x i64> %shuffle.i
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}
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define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) #0 {
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; CHECK-LABEL: test_vector_copy_dup_dv2D:
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; CHECK-NEXT: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #8
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; CHECK-NEXT: ret
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%vget_lane = extractelement <2 x i64> %c, i32 1
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%vset_lane = insertelement <1 x i64> undef, i64 %vget_lane, i32 0
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ret <1 x i64> %vset_lane
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}
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; Undefined behaviour, so we really don't care what actually gets emitted, just
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; as long as we don't crash (since it could be dynamically unreachable).
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define i32 @test_out_of_range_extract(<4 x i32> %vec) {
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; CHECK-LABEL: test_out_of_range_extract:
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; CHECK: ret
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%elt = extractelement <4 x i32> %vec, i32 4
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ret i32 %elt
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}
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; Undefined behaviour, so we really don't care what actually gets emitted, just
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; as long as we don't crash (since it could be dynamically unreachable).
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define void @test_out_of_range_insert(<4 x i32> %vec, i32 %elt) {
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; CHECK-LABEL: test_out_of_range_insert:
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; CHECK: ret
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insertelement <4 x i32> %vec, i32 %elt, i32 4
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ret void
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}
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attributes #0 = { nounwind }
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