llvm-mirror/test/CodeGen/ARM/fpcmp-f64-neon-opt.ll
Renato Golin cd30ecdc65 Do not emit intermediate register for zero FP immediate
This updates check for double precision zero floating point constant to allow
use of instruction with immediate value rather than temporary register.
Currently "a == 0.0", where "a" is of "double" type generates:

vmov.i32        d16, #0x0
vcmpe.f64       d0, d16

With this change it becomes:

vcmpe.f64        d0, #0

Patch by Sergey Dmitrouk.

llvm-svn: 220486
2014-10-23 15:31:50 +00:00

13 lines
380 B
LLVM

; RUN: llc -mtriple=linux-arm-gnueabihf -mattr=+neon %s -o - | FileCheck %s
; Check that no intermediate integer register is used.
define i32 @no-intermediate-register-for-zero-imm(double %x) #0 {
entry:
; CHECK-LABEL: no-intermediate-register-for-zero-imm
; CHECK-NOT: vmov
; CHECK: vcmp
%cmp = fcmp une double %x, 0.000000e+00
%conv = zext i1 %cmp to i32
ret i32 %conv
}