llvm-mirror/lib/Target/Sparc
Daniel Cederman fa32e290b7 [Sparc] Add support for 13-bit PIC
Summary: When compiling with -fpic, in contrast to -fPIC, use only the
immediate field to index into the GOT. This saves space if the GOT is
known to be small. The linker will warn if the GOT is too large for
this method.

Reviewers: jyknight, venkatra

Reviewed By: jyknight

Subscribers: brad, fedor.sergeev, jrtc27, llvm-commits

Differential Revision: https://reviews.llvm.org/D47136

llvm-svn: 334383
2018-06-11 05:50:08 +00:00
..
AsmParser [Sparc] Add support for 13-bit PIC 2018-06-11 05:50:08 +00:00
Disassembler Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
InstPrinter
MCTargetDesc [Sparc] Add support for 13-bit PIC 2018-06-11 05:50:08 +00:00
TargetInfo Add backend name to Target to enable runtime info to be fed back into TableGen 2017-11-15 23:55:44 +00:00
CMakeLists.txt Consistently sort add_subdirectory calls in lib/Target/*/CMakeLists.txt 2018-04-23 12:49:34 +00:00
DelaySlotFiller.cpp [DebugInfo] Examine all uses of isDebugValue() for debug instructions. 2018-05-09 02:42:00 +00:00
LeonFeatures.td Revert "This pass, fixing an erratum in some LEON 2 processors..." 2018-04-20 07:53:27 +00:00
LeonPasses.cpp [SPARC] Clean up the support for disabling fsmuld and fmuls instructions. 2017-07-20 20:09:11 +00:00
LeonPasses.h [SPARC] Clean up the support for disabling fsmuld and fmuls instructions. 2017-07-20 20:09:11 +00:00
LLVMBuild.txt
README.txt
Sparc.h [LegacyPassManager] Remove TargetMachine constructors 2017-05-18 17:21:13 +00:00
Sparc.td Revert "This pass, fixing an erratum in some LEON 2 processors..." 2018-04-20 07:53:27 +00:00
SparcAsmPrinter.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
SparcCallingConv.td
SparcFrameLowering.cpp [Sparc] Account for bias in stack readjustment 2018-01-29 12:10:32 +00:00
SparcFrameLowering.h Move TargetFrameLowering.h to CodeGen where it's implemented 2017-11-03 22:32:11 +00:00
SparcInstr64Bit.td
SparcInstrAliases.td [Sparc] Add mnemonic aliases for flush, stb, stba, sth, and stha 2018-05-23 08:26:49 +00:00
SparcInstrFormats.td
SparcInstrInfo.cpp [DebugInfo] Examine all uses of isDebugValue() for debug instructions. 2018-05-09 02:42:00 +00:00
SparcInstrInfo.h Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
SparcInstrInfo.td [Sparc] Use synthetic instruction clr to zero register instead of sethi 2018-04-20 07:47:12 +00:00
SparcInstrVIS.td Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversion 2017-12-11 22:25:04 +00:00
SparcISelDAGToDAG.cpp Revert "This pass, fixing an erratum in some LEON 2 processors..." 2018-04-20 07:53:27 +00:00
SparcISelLowering.cpp [Sparc] Add support for 13-bit PIC 2018-06-11 05:50:08 +00:00
SparcISelLowering.h Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversion 2017-12-11 22:25:04 +00:00
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcMCInstLower.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
SparcRegisterInfo.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
SparcRegisterInfo.h [Sparc] Return true in enableMultipleCopyHints(). 2018-02-24 08:24:31 +00:00
SparcRegisterInfo.td [SPARC] Support 'f' and 'e' inline asm constraints. 2017-05-12 15:59:10 +00:00
SparcSchedule.td [Sparc] Remove execute permissions from non-executable text files 2017-05-17 11:05:20 +00:00
SparcSubtarget.cpp Revert "This pass, fixing an erratum in some LEON 2 processors..." 2018-04-20 07:53:27 +00:00
SparcSubtarget.h Revert "This pass, fixing an erratum in some LEON 2 processors..." 2018-04-20 07:53:27 +00:00
SparcTargetMachine.cpp Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine" 2017-10-12 22:57:28 +00:00
SparcTargetMachine.h Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine" 2017-10-12 22:57:28 +00:00
SparcTargetObjectFile.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
SparcTargetObjectFile.h [Solaris] emit .init_array instead of .ctors on Solaris (Sparc/x86) 2017-06-21 20:36:32 +00:00
SparcTargetStreamer.h

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Use %g0 directly to materialize 0. No instruction is required.