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a309a8b1e0
The goal of this patch is to address most of PR36874. To fully fix PR36874 we need to split the "InstructionInfo" view from the "SummaryView". That would make easy to check the latency and rthroughput as well. The patch reuses all the logic from ResourcePressureView to print out the "instruction tables". We have an entry for every instruction in the input sequence. Each entry reports the theoretical resource pressure distribution. Resource pressure is uniformly distributed across all the processor resource units of a group. At the moment, the backend pipeline is not configurable, so the only way to fix this is by creating a different driver that simply sends instruction events to the resource pressure view. That means, we don't use the Backend interface. Instead, it is simpler to just have a different code-path for when flag -instruction-tables is specified. Once Clement addresses bug 36663, then we can port the "instruction tables" logic into a stage of our configurable pipeline. Updated the BtVer2 test cases (thanks Simon for the help). Now we pass flag -instruction-tables to each modified test. Differential Revision: https://reviews.llvm.org/D44839 llvm-svn: 328487
68 lines
2.4 KiB
C++
68 lines
2.4 KiB
C++
//===--------------------- InstrBuilder.h -----------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// A builder class for instructions that are statically analyzed by llvm-mca.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TOOLS_LLVM_MCA_INSTRBUILDER_H
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#define LLVM_TOOLS_LLVM_MCA_INSTRBUILDER_H
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#include "Instruction.h"
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#include "Support.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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namespace mca {
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class DispatchUnit;
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/// \brief A builder class that knows how to construct Instruction objects.
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///
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/// Every llvm-mca Instruction is described by an object of class InstrDesc.
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/// An InstrDesc describes which registers are read/written by the instruction,
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/// as well as the instruction latency and hardware resources consumed.
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///
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/// This class is used by the tool to construct Instructions and instruction
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/// descriptors (i.e. InstrDesc objects).
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/// Information from the machine scheduling model is used to identify processor
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/// resources that are consumed by an instruction.
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class InstrBuilder {
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const llvm::MCSubtargetInfo &STI;
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const llvm::MCInstrInfo &MCII;
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llvm::SmallVector<uint64_t, 8> ProcResourceMasks;
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llvm::DenseMap<unsigned short, std::unique_ptr<const InstrDesc>> Descriptors;
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void createInstrDescImpl(const llvm::MCInst &MCI);
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public:
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InstrBuilder(const llvm::MCSubtargetInfo &sti, const llvm::MCInstrInfo &mcii)
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: STI(sti), MCII(mcii),
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ProcResourceMasks(STI.getSchedModel().getNumProcResourceKinds()) {
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computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks);
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}
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const InstrDesc &getOrCreateInstrDesc(const llvm::MCInst &MCI);
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// Returns an array of processor resource masks.
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// Masks are computed by function mca::computeProcResourceMasks. see
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// Support.h for a description of how masks are computed and how masks can be
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// used to solve set membership problems.
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llvm::ArrayRef<uint64_t> getProcResourceMasks() const {
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return ProcResourceMasks;
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}
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std::unique_ptr<Instruction> createInstruction(unsigned Idx,
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const llvm::MCInst &MCI);
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};
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} // namespace mca
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#endif
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