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e68a099bb7
Summary: The bug was that microMIPS's [ls]w[lr]e instructions claimed to support a 12-bit offset when it is only 9-bit. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18434 llvm-svn: 265010
24 lines
1.9 KiB
ArmAsm
24 lines
1.9 KiB
ArmAsm
# Instructions that are invalid
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#
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# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \
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# RUN: 2>%t1
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# RUN: FileCheck %s < %t1
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.set noat
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ldl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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ldr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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sdl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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sdr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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ldle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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ldre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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sdle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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sdre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
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lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
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lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
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swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
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swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
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