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6372fe1697
Improve computeZeroableShuffleElements to be able to peek through bitcasts to extract zero/undef values from BUILD_VECTOR nodes of different element sizes to the shuffle mask. Differential Revision: http://reviews.llvm.org/D14261 llvm-svn: 263906
259 lines
10 KiB
LLVM
259 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
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define <4 x float> @shuffle_v4f32_0z27(<4 x float> %x, <4 x float> %a) {
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; SSE-LABEL: shuffle_v4f32_0z27:
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; SSE: # BB#0:
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; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[2]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4f32_0z27:
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; AVX: # BB#0:
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; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[2]
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; AVX-NEXT: retq
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%vecext = extractelement <4 x float> %x, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
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%vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
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%vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
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ret <4 x float> %vecinit5
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}
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define <4 x float> @shuffle_v4f32_0zz4(<4 x float> %xyzw, <4 x float> %abcd) {
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; SSE-LABEL: shuffle_v4f32_0zz4:
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; SSE: # BB#0:
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; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4f32_0zz4:
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; AVX: # BB#0:
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; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[0]
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; AVX-NEXT: retq
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%vecext = extractelement <4 x float> %xyzw, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
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%vecinit2 = insertelement <4 x float> %vecinit1, float 0.000000e+00, i32 2
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%vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %abcd, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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ret <4 x float> %vecinit4
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}
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define <4 x float> @shuffle_v4f32_0z24(<4 x float> %xyzw, <4 x float> %abcd) {
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; SSE-LABEL: shuffle_v4f32_0z24:
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; SSE: # BB#0:
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; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4f32_0z24:
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; AVX: # BB#0:
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; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[0]
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; AVX-NEXT: retq
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%vecext = extractelement <4 x float> %xyzw, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
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%vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %xyzw, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
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%vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %abcd, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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ret <4 x float> %vecinit5
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}
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define <4 x float> @shuffle_v4f32_0zz0(float %a) {
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; SSE-LABEL: shuffle_v4f32_0zz0:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm1, %xmm1
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; SSE-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1,1,0]
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4f32_0zz0:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,0]
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; AVX-NEXT: retq
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%vecinit = insertelement <4 x float> undef, float %a, i32 0
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%vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
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%vecinit2 = insertelement <4 x float> %vecinit1, float 0.000000e+00, i32 2
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%vecinit3 = insertelement <4 x float> %vecinit2, float %a, i32 3
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ret <4 x float> %vecinit3
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}
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define <4 x float> @shuffle_v4f32_0z6z(<4 x float> %A, <4 x float> %B) {
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; SSE-LABEL: shuffle_v4f32_0z6z:
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; SSE: # BB#0:
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; SSE-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffle_v4f32_0z6z:
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; AVX: # BB#0:
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; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
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; AVX-NEXT: retq
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%vecext = extractelement <4 x float> %A, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
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%vecext2 = extractelement <4 x float> %B, i32 2
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%vecinit3 = insertelement <4 x float> %vecinit1, float %vecext2, i32 2
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%vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
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ret <4 x float> %vecinit4
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}
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define <4 x float> @insertps_undef_input0(<4 x float> %a0, <4 x float> %a1) {
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; SSE-LABEL: insertps_undef_input0:
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; SSE: # BB#0:
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; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,xmm1[0],zero,zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: insertps_undef_input0:
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; AVX: # BB#0:
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; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm1[0],zero,zero
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; AVX-NEXT: retq
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%res0 = fadd <4 x float> %a0, <float 1.0, float 1.0, float 1.0, float 1.0>
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%res1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %res0, <4 x float> %a1, i8 21)
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%res2 = shufflevector <4 x float> %res1, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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ret <4 x float> %res2
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}
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define <4 x float> @insertps_undef_input1(<4 x float> %a0, <4 x float> %a1) {
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; SSE-LABEL: insertps_undef_input1:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm1, %xmm1
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; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: insertps_undef_input1:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
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; AVX-NEXT: retq
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%res0 = fadd <4 x float> %a1, <float 1.0, float 1.0, float 1.0, float 1.0>
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%res1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %res0, i8 21)
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%res2 = shufflevector <4 x float> %res1, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
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ret <4 x float> %res2
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}
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define <4 x float> @insertps_zero_from_v2f64(<4 x float> %a0, <2 x double>* %a1) nounwind {
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; SSE-LABEL: insertps_zero_from_v2f64:
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; SSE: # BB#0:
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; SSE-NEXT: movapd (%rdi), %xmm1
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; SSE-NEXT: addpd {{.*}}(%rip), %xmm1
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; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
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; SSE-NEXT: movapd %xmm1, (%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: insertps_zero_from_v2f64:
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; AVX: # BB#0:
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; AVX-NEXT: vmovapd (%rdi), %xmm1
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; AVX-NEXT: vaddpd {{.*}}(%rip), %xmm1, %xmm1
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; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
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; AVX-NEXT: vmovapd %xmm1, (%rdi)
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; AVX-NEXT: retq
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%1 = load <2 x double>, <2 x double>* %a1
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%2 = bitcast <2 x double> <double 1.0, double 2.0> to <4 x float>
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%3 = fadd <2 x double> %1, <double 1.0, double 2.0>
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%4 = shufflevector <4 x float> %a0, <4 x float> %2, <4 x i32> <i32 6, i32 2, i32 2, i32 3>
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store <2 x double> %3, <2 x double> *%a1
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ret <4 x float> %4
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}
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define <4 x float> @insertps_zero_from_v2i64(<4 x float> %a0, <2 x i64>* %a1) nounwind {
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; SSE-LABEL: insertps_zero_from_v2i64:
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; SSE: # BB#0:
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; SSE-NEXT: movdqa (%rdi), %xmm1
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; SSE-NEXT: paddq {{.*}}(%rip), %xmm1
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; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
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; SSE-NEXT: movdqa %xmm1, (%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: insertps_zero_from_v2i64:
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; AVX: # BB#0:
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; AVX-NEXT: vmovdqa (%rdi), %xmm1
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; AVX-NEXT: vpaddq {{.*}}(%rip), %xmm1, %xmm1
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; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
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; AVX-NEXT: vmovdqa %xmm1, (%rdi)
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; AVX-NEXT: retq
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%1 = load <2 x i64>, <2 x i64>* %a1
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%2 = bitcast <2 x i64> <i64 1, i64 -2> to <4 x float>
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%3 = add <2 x i64> %1, <i64 1, i64 -2>
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%4 = shufflevector <4 x float> %a0, <4 x float> %2, <4 x i32> <i32 5, i32 2, i32 2, i32 3>
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store <2 x i64> %3, <2 x i64> *%a1
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ret <4 x float> %4
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}
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define <4 x float> @insertps_zero_from_v8i16(<4 x float> %a0, <8 x i16>* %a1) nounwind {
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; SSE-LABEL: insertps_zero_from_v8i16:
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; SSE: # BB#0:
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; SSE-NEXT: movdqa (%rdi), %xmm1
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; SSE-NEXT: paddw {{.*}}(%rip), %xmm1
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; SSE-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
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; SSE-NEXT: movdqa %xmm1, (%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: insertps_zero_from_v8i16:
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; AVX: # BB#0:
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; AVX-NEXT: vmovdqa (%rdi), %xmm1
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; AVX-NEXT: vpaddw {{.*}}(%rip), %xmm1, %xmm1
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; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[2,2,3]
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; AVX-NEXT: vmovdqa %xmm1, (%rdi)
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; AVX-NEXT: retq
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%1 = load <8 x i16>, <8 x i16>* %a1
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%2 = bitcast <8 x i16> <i16 0, i16 0, i16 1, i16 1, i16 2, i16 2, i16 3, i16 3> to <4 x float>
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%3 = add <8 x i16> %1, <i16 0, i16 0, i16 1, i16 1, i16 2, i16 2, i16 3, i16 3>
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%4 = shufflevector <4 x float> %a0, <4 x float> %2, <4 x i32> <i32 4, i32 2, i32 2, i32 3>
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store <8 x i16> %3, <8 x i16> *%a1
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ret <4 x float> %4
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}
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define <4 x float> @consecutive_load_insertps_04zz(float* %p) {
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; SSE-LABEL: consecutive_load_insertps_04zz:
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; SSE: # BB#0:
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; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: consecutive_load_insertps_04zz:
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; AVX: # BB#0:
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; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX-NEXT: retq
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%p0 = getelementptr inbounds float, float* %p, i64 1
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%p1 = getelementptr inbounds float, float* %p, i64 2
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%s0 = load float, float* %p0
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%s1 = load float, float* %p1
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%v0 = insertelement <4 x float> undef, float %s0, i32 0
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%v1 = insertelement <4 x float> undef, float %s1, i32 0
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v0, <4 x float> %v1, i8 28)
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ret <4 x float> %res
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}
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define float @extract_zero_insertps_z0z7(<4 x float> %a0, <4 x float> %a1) {
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; SSE-LABEL: extract_zero_insertps_z0z7:
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; SSE: # BB#0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: extract_zero_insertps_z0z7:
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; AVX: # BB#0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 21)
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%ext = extractelement <4 x float> %res, i32 0
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ret float %ext
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}
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define float @extract_lane_insertps_5123(<4 x float> %a0, <4 x float> *%p1) {
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; SSE-LABEL: extract_lane_insertps_5123:
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; SSE: # BB#0:
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; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: extract_lane_insertps_5123:
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; AVX: # BB#0:
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; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX-NEXT: retq
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%a1 = load <4 x float>, <4 x float> *%p1
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 128)
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%ext = extractelement <4 x float> %res, i32 0
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ret float %ext
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}
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declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounwind readnone
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