llvm-mirror/test/MC/AMDGPU
Matt Arsenault c2c2a10170 AMDGPU: Fix handling of 16-bit immediates
Since 32-bit instructions with 32-bit input immediate behavior
are used to materialize 16-bit constants in 32-bit registers
for 16-bit instructions, determining the legality based
on the size is incorrect. Change operands to have the size
specified in the type.

Also adds a workaround for a disassembler bug that
produces an immediate MCOperand for an operand that
is supposed to be OPERAND_REGISTER.

The assembler appears to accept out of bounds immediates and
truncates them, but this seems to be an issue for 32-bit
already.

llvm-svn: 289306
2016-12-10 00:39:12 +00:00
..
regression
buffer_wbinv1l_vol_vi.s
ds-err.s
ds.s
exp-err.s AMDGPU: Assembler support for exp 2016-12-05 20:42:41 +00:00
exp.s AMDGPU: Assembler support for exp 2016-12-05 20:42:41 +00:00
expressions.s
flat-scratch.s
flat.s
hsa_code_object_isa_noargs.s
hsa-exp.s
hsa-text.s
hsa.s
labels-branch.s
lit.local.cfg
literal16-err.s AMDGPU: Fix handling of 16-bit immediates 2016-12-10 00:39:12 +00:00
literal16.s AMDGPU: Fix handling of 16-bit immediates 2016-12-10 00:39:12 +00:00
literals.s
macro-examples.s
max-branch-distance.s
mimg.s
mubuf.s
out-of-range-registers.s
reg-syntax-extra.s
reloc.s
smem-err.s AMDGPU: Disallow exec as SMEM instruction operand 2016-11-29 19:39:53 +00:00
smem.s AMDGPU: Allow TBA, TMA, TTMP* registers with SMEM instructions 2016-12-09 17:49:11 +00:00
smrd-err.s
smrd.s AMDGPU: Allow TBA, TMA, TTMP* registers with SMEM instructions 2016-12-09 17:49:11 +00:00
sop1-err.s
sop1.s
sop2.s
sopc-err.s
sopc.s
sopk-err.s
sopk.s
sopp-err.s
sopp.s
symbol_special.s
trap.s
vop1.s
vop2-err.s
vop2.s AMDGPU: Fix handling of 16-bit immediates 2016-12-10 00:39:12 +00:00
vop3-convert.s
vop3-errs.s
vop3-vop1-nosrc.s
vop3.s
vop_dpp_expr.s
vop_dpp.s
vop_sdwa.s
vopc-errs.s
vopc.s