llvm/test/CodeGen/X86/widen_conv-4.ll

; RUN: llc < %s -march=x86 -mcpu=nehalem -mattr=+sse42 | FileCheck %s
; CHECK-NOT: cvtsi2ss

; unsigned to float v7i16 to v7f32

define void @convert(<7 x float>* %dst.addr, <7 x i16> %src) nounwind {
entry:
	%val = sitofp <7 x i16> %src to <7 x float>
	store <7 x float> %val, <7 x float>* %dst.addr
	ret void
}
Add mcpu to tests to prevent them from using AVX instructions on Sandy Bridge after r155618. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155696 91177308-0d34-0410-b5e6-96231b3b80d8 2012-04-27 07:11:58 +00:00			`; RUN: llc < %s -march=x86 -mcpu=nehalem -mattr=+sse42 \| FileCheck %s`
Enable element promotion type legalization by deafault. Changed tests which assumed that vectors are legalized by widening them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142152 91177308-0d34-0410-b5e6-96231b3b80d8 2011-10-16 20:31:33 +00:00			`; CHECK-NOT: cvtsi2ss`
Added some basic test cases for r61209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61210 91177308-0d34-0410-b5e6-96231b3b80d8 2008-12-18 20:05:58 +00:00
			`; unsigned to float v7i16 to v7f32`

			`define void @convert(<7 x float>* %dst.addr, <7 x i16> %src) nounwind {`
			`entry:`
			`%val = sitofp <7 x i16> %src to <7 x float>`
			`store <7 x float> %val, <7 x float>* %dst.addr`
			`ret void`
			`}`