llvm/test/CodeGen/Mips/tls16.ll

; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PIC16

@a = thread_local global i32 4, align 4

define i32 @foo() nounwind readonly {
entry:
  %0 = load i32, i32* @a, align 4
; PIC16:	lw	${{[0-9]+}}, %call16(__tls_get_addr)(${{[0-9]+}})
; PIC16:	addiu	${{[0-9]+}}, %tlsgd(a)
  ret i32 %0
}
[mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250407 91177308-0d34-0410-b5e6-96231b3b80d8 2015-10-15 14:34:23 +00:00			`; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s \| FileCheck %s -check-prefix=PIC16`
implement mips16 tls global addr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166827 91177308-0d34-0410-b5e6-96231b3b80d8 2012-10-26 22:57:32 +00:00
			`@a = thread_local global i32 4, align 4`

			`define i32 @foo() nounwind readonly {`
			`entry:`
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=\|:\|^)\sload (?:atomic )?(?:volatile )?(.?))(\| addrspace\(\d+\) )\($\| (?:%\|@\|null\|undef\|blockaddress\|getelementptr\|addrspacecast\|bitcast\|inttoptr\|\[\[[a-zA-Z]\|\{\{).$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8 2015-02-27 21:17:42 +00:00			`%0 = load i32, i32* @a, align 4`
implement mips16 tls global addr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166827 91177308-0d34-0410-b5e6-96231b3b80d8 2012-10-26 22:57:32 +00:00			`; PIC16: lw ${{[0-9]+}}, %call16(__tls_get_addr)(${{[0-9]+}})`
			`; PIC16: addiu ${{[0-9]+}}, %tlsgd(a)`
			`ret i32 %0`
			`}`