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57 lines
3.1 KiB
ArmAsm
57 lines
3.1 KiB
ArmAsm
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// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s
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// Check that the assembler can handle the documented syntax for AArch64
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//------------------------------------------------------------------------------
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// Instructions across vector registers
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//------------------------------------------------------------------------------
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tbl v0.8b, {v1.16b}, v2.8b
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tbl v0.8b, {v1.16b, v2.16b}, v2.8b
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tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b
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tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b
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tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b
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// CHECK: tbl v0.8b, {v1.16b}, v2.8b // encoding: [0x20,0x00,0x02,0x0e]
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// CHECK: tbl v0.8b, {v1.16b, v2.16b}, v2.8b // encoding: [0x20,0x20,0x02,0x0e]
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// CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // encoding: [0x20,0x40,0x02,0x0e]
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// CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b // encoding: [0x20,0x60,0x02,0x0e]
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// CHECK: tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b // encoding: [0xe0,0x63,0x02,0x0e]
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tbl v0.16b, {v1.16b}, v2.16b
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tbl v0.16b, {v1.16b, v2.16b}, v2.16b
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tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b
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tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b
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tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b
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// CHECK: tbl v0.16b, {v1.16b}, v2.16b // encoding: [0x20,0x00,0x02,0x4e]
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// CHECK: tbl v0.16b, {v1.16b, v2.16b}, v2.16b // encoding: [0x20,0x20,0x02,0x4e]
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// CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b // encoding: [0x20,0x40,0x02,0x4e]
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// CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b // encoding: [0x20,0x60,0x02,0x4e]
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// CHECK: tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b // encoding: [0xc0,0x63,0x02,0x4e]
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tbx v0.8b, {v1.16b}, v2.8b
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tbx v0.8b, {v1.16b, v2.16b}, v2.8b
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tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b
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tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b
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tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b
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// CHECK: tbx v0.8b, {v1.16b}, v2.8b // encoding: [0x20,0x10,0x02,0x0e]
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// CHECK: tbx v0.8b, {v1.16b, v2.16b}, v2.8b // encoding: [0x20,0x30,0x02,0x0e]
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// CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // encoding: [0x20,0x50,0x02,0x0e]
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// CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b // encoding: [0x20,0x70,0x02,0x0e]
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// CHECK: tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b // encoding: [0xe0,0x73,0x02,0x0e]
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tbx v0.16b, {v1.16b}, v2.16b
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tbx v0.16b, {v1.16b, v2.16b}, v2.16b
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tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b
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tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b
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tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b
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// CHECK: tbx v0.16b, {v1.16b}, v2.16b // encoding: [0x20,0x10,0x02,0x4e]
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// CHECK: tbx v0.16b, {v1.16b, v2.16b}, v2.16b // encoding: [0x20,0x30,0x02,0x4e]
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// CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b // encoding: [0x20,0x50,0x02,0x4e]
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// CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b // encoding: [0x20,0x70,0x02,0x4e]
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// CHECK: tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b // encoding: [0xc0,0x73,0x02,0x4e]
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