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llvm/test/MC/ARM/arm-ldrd.s

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[ARM] Use FileCheck instead of grep for ARM LDRD negative tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191683 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 17:31:26 +00:00
// RUN: not llvm-mc -arch arm -mattr=+v5te %s 2>&1 | FileCheck %s
//
ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands. As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints: LDRD<c> <Rt>, <Rt2>, ... (a) Rt must be even-numbered and not r14 (b) Rt2 must be R(t+1) If those two constraints are not met the result of executing the instruction will be unpredictable. Constraint (b) was already enforced, this commit adds support for constraint (a). Fixes rdar://14479793. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191520 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 13:28:17 +00:00
// rdar://14479793
ldrd r1, r2, [pc, #0]
ldrd r1, r2, [r3, #4]
ldrd r1, r2, [r3], #4
ldrd r1, r2, [r3, #4]!
ldrd r1, r2, [r3, -r4]!
ldrd r1, r2, [r3, r4]
ldrd r1, r2, [r3], r4
[ARM] Use FileCheck instead of grep for ARM LDRD negative tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191683 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 17:31:26 +00:00
// CHECK: error: Rt must be even-numbered
// CHECK: error: Rt must be even-numbered
// CHECK: error: Rt must be even-numbered
// CHECK: error: Rt must be even-numbered
// CHECK: error: Rt must be even-numbered
// CHECK: error: Rt must be even-numbered
// CHECK: error: Rt must be even-numbered
ldrd r0, r3, [pc, #0]
ldrd r0, r3, [r4, #4]
ldrd r0, r3, [r4], #4
ldrd r0, r3, [r4, #4]!
ldrd r0, r3, [r4, -r5]!
ldrd r0, r3, [r4, r5]
[ARM] Assembler: Add more negative tests for ARM LDRD. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191664 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 13:04:22 +00:00
ldrd r0, r3, [r4], r5
[ARM] Use FileCheck instead of grep for ARM LDRD negative tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191683 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 17:31:26 +00:00
// CHECK: error: destination operands must be sequential
// CHECK: error: destination operands must be sequential
// CHECK: error: destination operands must be sequential
// CHECK: error: destination operands must be sequential
// CHECK: error: destination operands must be sequential
// CHECK: error: destination operands must be sequential
// CHECK: error: destination operands must be sequential
ldrd lr, pc, [pc, #0]
ldrd lr, pc, [r3, #4]
ldrd lr, pc, [r3], #4
ldrd lr, pc, [r3, #4]!
ldrd lr, pc, [r3, -r4]!
ldrd lr, pc, [r3, r4]
ldrd lr, pc, [r3], r4
// CHECK: error: Rt can't be R14
// CHECK: error: Rt can't be R14
// CHECK: error: Rt can't be R14
// CHECK: error: Rt can't be R14
// CHECK: error: Rt can't be R14
// CHECK: error: Rt can't be R14
// CHECK: error: Rt can't be R14
[ARM] Assembler: ARM LDRD with writeback requires the base register to be different from the destination registers. See ARM ARM A8.8.72. Violating this constraint results in unpredictable behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191678 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 16:11:48 +00:00
ldrd r0, r1, [r0], #4
ldrd r0, r1, [r1], #4
ldrd r0, r1, [r0, #4]!
ldrd r0, r1, [r1, #4]!
[ARM] Use FileCheck instead of grep for ARM LDRD negative tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191683 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 17:31:26 +00:00
// CHECK: error: base register needs to be different from destination registers
// CHECK: error: base register needs to be different from destination registers
// CHECK: error: base register needs to be different from destination registers
// CHECK: error: base register needs to be different from destination registers
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