llvm/test/CodeGen/X86/inline-asm-flag-clobber.ll

; RUN: llc -march=x86-64 < %s | FileCheck %s
; PR3701

define i64 @t(i64* %arg) nounwind {
	br i1 true, label %1, label %5

; <label>:1		; preds = %0
	%2 = icmp eq i64* null, %arg		; <i1> [#uses=1]
	%3 = tail call i64* asm sideeffect "movl %fs:0,$0", "=r,~{dirflag},~{fpsr},~{flags}"() nounwind		; <%struct.thread*> [#uses=0]
; CHECK: test
; CHECK-NEXT: j
	br i1 %2, label %4, label %5

; <label>:4		; preds = %1
	ret i64 1

; <label>:5		; preds = %1
	ret i64 0
}
Eliminate uses of %prcontext. - I'd appreciate it if someone else eyeballs my changes to make sure I captured the intent of the test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81083 91177308-0d34-0410-b5e6-96231b3b80d8 2009-09-05 11:35:16 +00:00			`; RUN: llc -march=x86-64 < %s \| FileCheck %s`
Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65996 91177308-0d34-0410-b5e6-96231b3b80d8 2009-03-04 01:41:49 +00:00			`; PR3701`

			`define i64 @t(i64* %arg) nounwind {`
			`br i1 true, label %1, label %5`

			`; <label>:1 ; preds = %0`
			`%2 = icmp eq i64* null, %arg ; <i1> [#uses=1]`
			`%3 = tail call i64* asm sideeffect "movl %fs:0,$0", "=r,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%struct.thread*> [#uses=0]`
Eliminate uses of %prcontext. - I'd appreciate it if someone else eyeballs my changes to make sure I captured the intent of the test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81083 91177308-0d34-0410-b5e6-96231b3b80d8 2009-09-05 11:35:16 +00:00			`; CHECK: test`
			`; CHECK-NEXT: j`
Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65996 91177308-0d34-0410-b5e6-96231b3b80d8 2009-03-04 01:41:49 +00:00			`br i1 %2, label %4, label %5`

			`; <label>:4 ; preds = %1`
			`ret i64 1`

			`; <label>:5 ; preds = %1`
			`ret i64 0`
			`}`