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llvm/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll

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Fix the handling of partial redefines in the fast register allocator. A partial redefine needs to be treated like a tied operand, and the register must be reloaded while processing use operands. This fixes a bug where partially redefined registers were processed as normal defs with a reload added. The reload could clobber another use operand if it was a kill that allowed register reuse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 19:15:30 +00:00
; RUN: llc < %s -O0 -mcpu=cortex-a8 | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
target triple = "thumbv7-apple-darwin10"
; This tests the fast register allocator's handling of partial redefines:
;
Reenable DAG combining for vector shuffles. It looks like it was temporarily disabled and then never turned back on again. Adjust some tests, one because this change avoids an unnecessary instruction, and the other to make it continue testing what it was intended to test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:38:12 +00:00
; %reg1028:dsub_0<def>, %reg1028:dsub_1<def> = VLD1q64 %reg1025...
; %reg1030:dsub_1<def> = COPY %reg1028:dsub_0<kill>
Fix the handling of partial redefines in the fast register allocator. A partial redefine needs to be treated like a tied operand, and the register must be reloaded while processing use operands. This fixes a bug where partially redefined registers were processed as normal defs with a reload added. The reload could clobber another use operand if it was a kill that allowed register reuse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 19:15:30 +00:00
;
Reenable DAG combining for vector shuffles. It looks like it was temporarily disabled and then never turned back on again. Adjust some tests, one because this change avoids an unnecessary instruction, and the other to make it continue testing what it was intended to test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:38:12 +00:00
; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial
; redef, it cannot also get %Q0.
Fix the handling of partial redefines in the fast register allocator. A partial redefine needs to be treated like a tied operand, and the register must be reloaded while processing use operands. This fixes a bug where partially redefined registers were processed as normal defs with a reload added. The reload could clobber another use operand if it was a kill that allowed register reuse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 19:15:30 +00:00
Fix test to be less sensitive of regalloc accidents git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 01:32:11 +00:00
; CHECK: vld1.64 {d0, d1}, [r{{.}}]
Reenable DAG combining for vector shuffles. It looks like it was temporarily disabled and then never turned back on again. Adjust some tests, one because this change avoids an unnecessary instruction, and the other to make it continue testing what it was intended to test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:38:12 +00:00
; CHECK-NOT: vld1.64 {d0, d1}
Fix the handling of partial redefines in the fast register allocator. A partial redefine needs to be treated like a tied operand, and the register must be reloaded while processing use operands. This fixes a bug where partially redefined registers were processed as normal defs with a reload added. The reload could clobber another use operand if it was a kill that allowed register reuse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 19:15:30 +00:00
; CHECK: vmov.f64 d3, d0
Reenable DAG combining for vector shuffles. It looks like it was temporarily disabled and then never turned back on again. Adjust some tests, one because this change avoids an unnecessary instruction, and the other to make it continue testing what it was intended to test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:38:12 +00:00
define i32 @test(i8* %arg) nounwind {
Fix the handling of partial redefines in the fast register allocator. A partial redefine needs to be treated like a tied operand, and the register must be reloaded while processing use operands. This fixes a bug where partially redefined registers were processed as normal defs with a reload added. The reload could clobber another use operand if it was a kill that allowed register reuse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 19:15:30 +00:00
entry:
Reenable DAG combining for vector shuffles. It looks like it was temporarily disabled and then never turned back on again. Adjust some tests, one because this change avoids an unnecessary instruction, and the other to make it continue testing what it was intended to test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:38:12 +00:00
%0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %arg)
%1 = shufflevector <2 x i64> undef, <2 x i64> %0, <2 x i32> <i32 1, i32 2>
store <2 x i64> %1, <2 x i64>* undef, align 16
Fix the handling of partial redefines in the fast register allocator. A partial redefine needs to be treated like a tied operand, and the register must be reloaded while processing use operands. This fixes a bug where partially redefined registers were processed as normal defs with a reload added. The reload could clobber another use operand if it was a kill that allowed register reuse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 19:15:30 +00:00
ret i32 undef
}
Reenable DAG combining for vector shuffles. It looks like it was temporarily disabled and then never turned back on again. Adjust some tests, one because this change avoids an unnecessary instruction, and the other to make it continue testing what it was intended to test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:38:12 +00:00
declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*) nounwind readonly
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