llvm/test/CodeGen/X86/x86-64-extend-shift.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
; Formerly there were two shifts.

define i64 @baz(i32 %A) nounwind {
; CHECK:  shlq  $49, %r
        %tmp1 = shl i32 %A, 17
        %tmp2 = zext i32 %tmp1 to i64
        %tmp3 = shl i64 %tmp2, 32
        ret i64 %tmp3
}
Reapply 122353-122355 with fixes. 122354 was wrong; the shift type was needed one place, the shift count type another. The transform in 123555 had the same problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122366 91177308-0d34-0410-b5e6-96231b3b80d8 2010-12-21 21:55:50 +00:00			`; RUN: llc < %s -mtriple=x86_64-apple-darwin \| FileCheck %s`
			`; Formerly there were two shifts.`

			`define i64 @baz(i32 %A) nounwind {`
Don't depend on the physreg coalescing order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130818 91177308-0d34-0410-b5e6-96231b3b80d8 2011-05-04 01:01:47 +00:00			`; CHECK: shlq $49, %r`
Reapply 122353-122355 with fixes. 122354 was wrong; the shift type was needed one place, the shift count type another. The transform in 123555 had the same problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122366 91177308-0d34-0410-b5e6-96231b3b80d8 2010-12-21 21:55:50 +00:00			`%tmp1 = shl i32 %A, 17`
			`%tmp2 = zext i32 %tmp1 to i64`
			`%tmp3 = shl i64 %tmp2, 32`
			`ret i64 %tmp3`
			`}`