llvm/test/CodeGen/ARM/str_pre-2.ll

; RUN: llc < %s -mtriple=arm-linux-gnu | grep {str.*\\!}
; RUN: llc < %s -mtriple=arm-linux-gnu | grep {ldr.*\\\[.*\], #4}

@b = external global i64*

define i64 @t(i64 %a) nounwind readonly {
entry:
	%0 = load i64** @b, align 4
	%1 = load i64* %0, align 4
	%2 = mul i64 %1, %a
	ret i64 %2
}
Eliminate more uses of llvm-as and llvm-dis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8 2009-09-09 00:09:15 +00:00			`; RUN: llc < %s -mtriple=arm-linux-gnu \| grep {str.*\\!}`
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98745 91177308-0d34-0410-b5e6-96231b3b80d8 2010-03-17 17:52:21 +00:00			`; RUN: llc < %s -mtriple=arm-linux-gnu \| grep {ldr.\\\[.\], #4}`
Fold preceding / trailing base inc / dec into the single load / store as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8 2009-06-03 06:14:58 +00:00
			`@b = external global i64*`

			`define i64 @t(i64 %a) nounwind readonly {`
			`entry:`
			`%0 = load i64** @b, align 4`
			`%1 = load i64* %0, align 4`
			`%2 = mul i64 %1, %a`
			`ret i64 %2`
			`}`