RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-11-28 14:10:55 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
915558e775
llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll

194 lines
8.0 KiB
LLVM
Raw Normal View History

Fix remaining lit tests which were failing when run on an Atom processor. Patches by Tyler Nowicki, Andy Zhang, and Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19 18:53:21 +00:00
; RUN: llc -mtriple=x86_64-darwin -mcpu=generic < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-darwin -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s
Eliminate uses of %prcontext. - I'd appreciate it if someone else eyeballs my changes to make sure I captured the intent of the test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81083 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-05 11:35:16 +00:00
Don't break the IV update in TLI::SimplifySetCC(). LSR always tries to make the ICmp in the loop latch use the incremented induction variable. This allows the induction variable to be kept in a single register. When the induction variable limit is equal to the stride, SimplifySetCC() would break LSR's hard work by transforming: (icmp (add iv, stride), stride) --> (cmp iv, 0) This forced us to use lea for the IC update, preventing the simpler incl+cmp. <rdar://problem/7643606> <rdar://problem/11184260> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154119 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05 20:30:20 +00:00
; CHECK: t:
Eliminate uses of %prcontext. - I'd appreciate it if someone else eyeballs my changes to make sure I captured the intent of the test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81083 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-05 11:35:16 +00:00
; CHECK: decq
PR13578: Teach MachineCSE that instructions that use a constant register can be CSE'd safely. This is common e.g. when doing rip-relative addressing on x86_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11 19:05:13 +00:00
; CHECK-NEXT: movl (%r9,%rax,4), %eax
Eliminate uses of %prcontext. - I'd appreciate it if someone else eyeballs my changes to make sure I captured the intent of the test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81083 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-05 11:35:16 +00:00
; CHECK-NEXT: jne
Teach LSR to optimize more loop exit compares, i.e. change them to use postinc iv value. Previously LSR would only optimize those which are in the loop latch block. However, if LSR can prove it is safe (and profitable), it's now possible to change those not in the latch blocks to use postinc values. Also, if the compare is the only use, LSR would place the iv increment instruction before the compare instead in the latch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71485 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-11 22:33:01 +00:00
Fix remaining lit tests which were failing when run on an Atom processor. Patches by Tyler Nowicki, Andy Zhang, and Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19 18:53:21 +00:00
; ATOM: t:
PR13578: Teach MachineCSE that instructions that use a constant register can be CSE'd safely. This is common e.g. when doing rip-relative addressing on x86_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-11 19:05:13 +00:00
; ATOM: movl (%r9,%rax,4), %eax
Fix remaining lit tests which were failing when run on an Atom processor. Patches by Tyler Nowicki, Andy Zhang, and Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19 18:53:21 +00:00
; ATOM-NEXT: decq
; ATOM-NEXT: jne
Teach LSR to optimize more loop exit compares, i.e. change them to use postinc iv value. Previously LSR would only optimize those which are in the loop latch block. However, if LSR can prove it is safe (and profitable), it's now possible to change those not in the latch blocks to use postinc values. Also, if the compare is the only use, LSR would place the iv increment instruction before the compare instead in the latch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71485 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-11 22:33:01 +00:00
@Te0 = external global [256 x i32] ; <[256 x i32]*> [#uses=5]
@Te1 = external global [256 x i32] ; <[256 x i32]*> [#uses=4]
@Te3 = external global [256 x i32] ; <[256 x i32]*> [#uses=2]
This test doesn't need the ssp attribute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105440 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04 00:14:48 +00:00
define void @t(i8* nocapture %in, i8* nocapture %out, i32* nocapture %rk, i32 %r) nounwind {
Teach LSR to optimize more loop exit compares, i.e. change them to use postinc iv value. Previously LSR would only optimize those which are in the loop latch block. However, if LSR can prove it is safe (and profitable), it's now possible to change those not in the latch blocks to use postinc values. Also, if the compare is the only use, LSR would place the iv increment instruction before the compare instead in the latch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71485 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-11 22:33:01 +00:00
entry:
%0 = load i32* %rk, align 4 ; <i32> [#uses=1]
%1 = getelementptr i32* %rk, i64 1 ; <i32*> [#uses=1]
%2 = load i32* %1, align 4 ; <i32> [#uses=1]
%tmp15 = add i32 %r, -1 ; <i32> [#uses=1]
%tmp.16 = zext i32 %tmp15 to i64 ; <i64> [#uses=2]
br label %bb
bb: ; preds = %bb1, %entry
%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %bb1 ] ; <i64> [#uses=3]
%s1.0 = phi i32 [ %2, %entry ], [ %56, %bb1 ] ; <i32> [#uses=2]
%s0.0 = phi i32 [ %0, %entry ], [ %43, %bb1 ] ; <i32> [#uses=2]
%tmp18 = shl i64 %indvar, 4 ; <i64> [#uses=4]
%rk26 = bitcast i32* %rk to i8* ; <i8*> [#uses=6]
%3 = lshr i32 %s0.0, 24 ; <i32> [#uses=1]
%4 = zext i32 %3 to i64 ; <i64> [#uses=1]
%5 = getelementptr [256 x i32]* @Te0, i64 0, i64 %4 ; <i32*> [#uses=1]
%6 = load i32* %5, align 4 ; <i32> [#uses=1]
%7 = lshr i32 %s1.0, 16 ; <i32> [#uses=1]
%8 = and i32 %7, 255 ; <i32> [#uses=1]
%9 = zext i32 %8 to i64 ; <i64> [#uses=1]
%10 = getelementptr [256 x i32]* @Te1, i64 0, i64 %9 ; <i32*> [#uses=1]
%11 = load i32* %10, align 4 ; <i32> [#uses=1]
%ctg2.sum2728 = or i64 %tmp18, 8 ; <i64> [#uses=1]
%12 = getelementptr i8* %rk26, i64 %ctg2.sum2728 ; <i8*> [#uses=1]
%13 = bitcast i8* %12 to i32* ; <i32*> [#uses=1]
%14 = load i32* %13, align 4 ; <i32> [#uses=1]
%15 = xor i32 %11, %6 ; <i32> [#uses=1]
%16 = xor i32 %15, %14 ; <i32> [#uses=3]
%17 = lshr i32 %s1.0, 24 ; <i32> [#uses=1]
%18 = zext i32 %17 to i64 ; <i64> [#uses=1]
%19 = getelementptr [256 x i32]* @Te0, i64 0, i64 %18 ; <i32*> [#uses=1]
%20 = load i32* %19, align 4 ; <i32> [#uses=1]
%21 = and i32 %s0.0, 255 ; <i32> [#uses=1]
%22 = zext i32 %21 to i64 ; <i64> [#uses=1]
%23 = getelementptr [256 x i32]* @Te3, i64 0, i64 %22 ; <i32*> [#uses=1]
%24 = load i32* %23, align 4 ; <i32> [#uses=1]
%ctg2.sum2930 = or i64 %tmp18, 12 ; <i64> [#uses=1]
%25 = getelementptr i8* %rk26, i64 %ctg2.sum2930 ; <i8*> [#uses=1]
%26 = bitcast i8* %25 to i32* ; <i32*> [#uses=1]
%27 = load i32* %26, align 4 ; <i32> [#uses=1]
%28 = xor i32 %24, %20 ; <i32> [#uses=1]
%29 = xor i32 %28, %27 ; <i32> [#uses=4]
%30 = lshr i32 %16, 24 ; <i32> [#uses=1]
%31 = zext i32 %30 to i64 ; <i64> [#uses=1]
%32 = getelementptr [256 x i32]* @Te0, i64 0, i64 %31 ; <i32*> [#uses=1]
%33 = load i32* %32, align 4 ; <i32> [#uses=2]
%exitcond = icmp eq i64 %indvar, %tmp.16 ; <i1> [#uses=1]
br i1 %exitcond, label %bb2, label %bb1
bb1: ; preds = %bb
%ctg2.sum31 = add i64 %tmp18, 16 ; <i64> [#uses=1]
%34 = getelementptr i8* %rk26, i64 %ctg2.sum31 ; <i8*> [#uses=1]
%35 = bitcast i8* %34 to i32* ; <i32*> [#uses=1]
%36 = lshr i32 %29, 16 ; <i32> [#uses=1]
%37 = and i32 %36, 255 ; <i32> [#uses=1]
%38 = zext i32 %37 to i64 ; <i64> [#uses=1]
%39 = getelementptr [256 x i32]* @Te1, i64 0, i64 %38 ; <i32*> [#uses=1]
%40 = load i32* %39, align 4 ; <i32> [#uses=1]
%41 = load i32* %35, align 4 ; <i32> [#uses=1]
%42 = xor i32 %40, %33 ; <i32> [#uses=1]
%43 = xor i32 %42, %41 ; <i32> [#uses=1]
%44 = lshr i32 %29, 24 ; <i32> [#uses=1]
%45 = zext i32 %44 to i64 ; <i64> [#uses=1]
%46 = getelementptr [256 x i32]* @Te0, i64 0, i64 %45 ; <i32*> [#uses=1]
%47 = load i32* %46, align 4 ; <i32> [#uses=1]
%48 = and i32 %16, 255 ; <i32> [#uses=1]
%49 = zext i32 %48 to i64 ; <i64> [#uses=1]
%50 = getelementptr [256 x i32]* @Te3, i64 0, i64 %49 ; <i32*> [#uses=1]
%51 = load i32* %50, align 4 ; <i32> [#uses=1]
%ctg2.sum32 = add i64 %tmp18, 20 ; <i64> [#uses=1]
%52 = getelementptr i8* %rk26, i64 %ctg2.sum32 ; <i8*> [#uses=1]
%53 = bitcast i8* %52 to i32* ; <i32*> [#uses=1]
%54 = load i32* %53, align 4 ; <i32> [#uses=1]
%55 = xor i32 %51, %47 ; <i32> [#uses=1]
%56 = xor i32 %55, %54 ; <i32> [#uses=1]
%indvar.next = add i64 %indvar, 1 ; <i64> [#uses=1]
br label %bb
bb2: ; preds = %bb
%tmp10 = shl i64 %tmp.16, 4 ; <i64> [#uses=2]
%ctg2.sum = add i64 %tmp10, 16 ; <i64> [#uses=1]
%tmp1213 = getelementptr i8* %rk26, i64 %ctg2.sum ; <i8*> [#uses=1]
%57 = bitcast i8* %tmp1213 to i32* ; <i32*> [#uses=1]
%58 = and i32 %33, -16777216 ; <i32> [#uses=1]
%59 = lshr i32 %29, 16 ; <i32> [#uses=1]
%60 = and i32 %59, 255 ; <i32> [#uses=1]
%61 = zext i32 %60 to i64 ; <i64> [#uses=1]
%62 = getelementptr [256 x i32]* @Te1, i64 0, i64 %61 ; <i32*> [#uses=1]
%63 = load i32* %62, align 4 ; <i32> [#uses=1]
%64 = and i32 %63, 16711680 ; <i32> [#uses=1]
%65 = or i32 %64, %58 ; <i32> [#uses=1]
%66 = load i32* %57, align 4 ; <i32> [#uses=1]
%67 = xor i32 %65, %66 ; <i32> [#uses=2]
%68 = lshr i32 %29, 8 ; <i32> [#uses=1]
%69 = zext i32 %68 to i64 ; <i64> [#uses=1]
%70 = getelementptr [256 x i32]* @Te0, i64 0, i64 %69 ; <i32*> [#uses=1]
%71 = load i32* %70, align 4 ; <i32> [#uses=1]
%72 = and i32 %71, -16777216 ; <i32> [#uses=1]
%73 = and i32 %16, 255 ; <i32> [#uses=1]
%74 = zext i32 %73 to i64 ; <i64> [#uses=1]
%75 = getelementptr [256 x i32]* @Te1, i64 0, i64 %74 ; <i32*> [#uses=1]
%76 = load i32* %75, align 4 ; <i32> [#uses=1]
%77 = and i32 %76, 16711680 ; <i32> [#uses=1]
%78 = or i32 %77, %72 ; <i32> [#uses=1]
%ctg2.sum25 = add i64 %tmp10, 20 ; <i64> [#uses=1]
%79 = getelementptr i8* %rk26, i64 %ctg2.sum25 ; <i8*> [#uses=1]
%80 = bitcast i8* %79 to i32* ; <i32*> [#uses=1]
%81 = load i32* %80, align 4 ; <i32> [#uses=1]
%82 = xor i32 %78, %81 ; <i32> [#uses=2]
%83 = lshr i32 %67, 24 ; <i32> [#uses=1]
%84 = trunc i32 %83 to i8 ; <i8> [#uses=1]
store i8 %84, i8* %out, align 1
%85 = lshr i32 %67, 16 ; <i32> [#uses=1]
%86 = trunc i32 %85 to i8 ; <i8> [#uses=1]
%87 = getelementptr i8* %out, i64 1 ; <i8*> [#uses=1]
store i8 %86, i8* %87, align 1
%88 = getelementptr i8* %out, i64 4 ; <i8*> [#uses=1]
%89 = lshr i32 %82, 24 ; <i32> [#uses=1]
%90 = trunc i32 %89 to i8 ; <i8> [#uses=1]
store i8 %90, i8* %88, align 1
%91 = lshr i32 %82, 16 ; <i32> [#uses=1]
%92 = trunc i32 %91 to i8 ; <i8> [#uses=1]
%93 = getelementptr i8* %out, i64 5 ; <i8*> [#uses=1]
store i8 %92, i8* %93, align 1
ret void
}
Don't break the IV update in TLI::SimplifySetCC(). LSR always tries to make the ICmp in the loop latch use the incremented induction variable. This allows the induction variable to be kept in a single register. When the induction variable limit is equal to the stride, SimplifySetCC() would break LSR's hard work by transforming: (icmp (add iv, stride), stride) --> (cmp iv, 0) This forced us to use lea for the IC update, preventing the simpler incl+cmp. <rdar://problem/7643606> <rdar://problem/11184260> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154119 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05 20:30:20 +00:00
; Check that DAGCombiner doesn't mess up the IV update when the exiting value
; is equal to the stride.
; It must not fold (cmp (add iv, 1), 1) --> (cmp iv, 0).
; CHECK: f:
; CHECK: %for.body
; CHECK: incl [[IV:%e..]]
; CHECK: cmpl $1, [[IV]]
; CHECK: jne
; CHECK: ret
Fix remaining lit tests which were failing when run on an Atom processor. Patches by Tyler Nowicki, Andy Zhang, and Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160520 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19 18:53:21 +00:00
; ATOM: f:
; ATOM: %for.body
; ATOM: incl [[IV:%e..]]
; ATOM: cmpl $1, [[IV]]
; ATOM: jne
; ATOM: ret
Don't break the IV update in TLI::SimplifySetCC(). LSR always tries to make the ICmp in the loop latch use the incremented induction variable. This allows the induction variable to be kept in a single register. When the induction variable limit is equal to the stride, SimplifySetCC() would break LSR's hard work by transforming: (icmp (add iv, stride), stride) --> (cmp iv, 0) This forced us to use lea for the IC update, preventing the simpler incl+cmp. <rdar://problem/7643606> <rdar://problem/11184260> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154119 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-05 20:30:20 +00:00
define i32 @f(i32 %i, i32* nocapture %a) nounwind uwtable readonly ssp {
entry:
%cmp4 = icmp eq i32 %i, 1
br i1 %cmp4, label %for.end, label %for.body.lr.ph
for.body.lr.ph: ; preds = %entry
%0 = sext i32 %i to i64
br label %for.body
for.body: ; preds = %for.body.lr.ph, %for.body
%indvars.iv = phi i64 [ %0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]
%bi.06 = phi i32 [ 0, %for.body.lr.ph ], [ %i.addr.0.bi.0, %for.body ]
%b.05 = phi i32 [ 0, %for.body.lr.ph ], [ %.b.0, %for.body ]
%arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
%1 = load i32* %arrayidx, align 4
%cmp1 = icmp ugt i32 %1, %b.05
%.b.0 = select i1 %cmp1, i32 %1, i32 %b.05
%2 = trunc i64 %indvars.iv to i32
%i.addr.0.bi.0 = select i1 %cmp1, i32 %2, i32 %bi.06
%indvars.iv.next = add i64 %indvars.iv, 1
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
%exitcond = icmp eq i32 %lftr.wideiv, 1
br i1 %exitcond, label %for.end, label %for.body
for.end: ; preds = %for.body, %entry
%bi.0.lcssa = phi i32 [ 0, %entry ], [ %i.addr.0.bi.0, %for.body ]
ret i32 %bi.0.lcssa
}
Reference in New Issue Copy Permalink