llvm/test/CodeGen/X86/vec_set-C.ll

; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq
; RUN: llc < %s -march=x86 -mattr=+sse2 | grep mov | count 1
; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd

define <2 x i64> @t1(i64 %x) nounwind  {
	%tmp8 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0
	ret <2 x i64> %tmp8
}
Eliminate more uses of llvm-as and llvm-dis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81290 91177308-0d34-0410-b5e6-96231b3b80d8 2009-09-08 23:54:48 +00:00			`; RUN: llc < %s -march=x86 -mattr=+sse2 \| grep movq`
			`; RUN: llc < %s -march=x86 -mattr=+sse2 \| grep mov \| count 1`
			`; RUN: llc < %s -march=x86-64 -mattr=+sse2 \| grep movd`
Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8 2008-05-08 00:57:18 +00:00
			`define <2 x i64> @t1(i64 %x) nounwind {`
			`%tmp8 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0`
			`ret <2 x i64> %tmp8`
			`}`