llvm/test/CodeGen/ARM/ispositive.ll

; RUN: llc < %s -march=arm | FileCheck %s

define i32 @test1(i32 %X) {
; CHECK: lsr{{.*}}#31
entry:
        icmp slt i32 %X, 0              ; <i1>:0 [#uses=1]
        zext i1 %0 to i32               ; <i32>:1 [#uses=1]
        ret i32 %1
}
Fix the rest of the ARM failures by converting them to FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85208 91177308-0d34-0410-b5e6-96231b3b80d8 2009-10-27 06:16:45 +00:00			`; RUN: llc < %s -march=arm \| FileCheck %s`
new testcase git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35882 91177308-0d34-0410-b5e6-96231b3b80d8 2007-04-11 05:32:13 +00:00
change test name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35904 91177308-0d34-0410-b5e6-96231b3b80d8 2007-04-11 15:24:04 +00:00			`define i32 @test1(i32 %X) {`
Update tests to handle MC-inst instruction printing of shift operations. The legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic is correct and preferred according the ARM documentation (A8.6.98). The former are pseudo-instructions for the latter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114221 91177308-0d34-0410-b5e6-96231b3b80d8 2010-09-17 21:58:46 +00:00			`; CHECK: lsr{{.*}}#31`
new testcase git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35882 91177308-0d34-0410-b5e6-96231b3b80d8 2007-04-11 05:32:13 +00:00			`entry:`
			`icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]`
			`zext i1 %0 to i32 ; <i32>:1 [#uses=1]`
			`ret i32 %1`
			`}`