llvm/test/CodeGen/X86/mmx-pinsrw.ll

; RUN: llc < %s  -mtriple=x86_64-linux -mcpu=corei7 | FileCheck %s
; PR2562

; CHECK: pinsr

external global i16		; <i16*>:0 [#uses=1]
external global <4 x i16>		; <<4 x i16>*>:1 [#uses=2]

declare void @abort()

define void @""() {
	load i16* @0		; <i16>:1 [#uses=1]
	load <4 x i16>* @1		; <<4 x i16>>:2 [#uses=1]
	insertelement <4 x i16> %2, i16 %1, i32 0		; <<4 x i16>>:3 [#uses=1]
	store <4 x i16> %3, <4 x i16>* @1
	ret void
}
Rewrite some tests with FileCHeck in X86 codegen - Revise previous patches of the same purpose by fixing ) grep <PA> \| not grep <PB> semantically is not the same as CHECK: <PA>{{^<PB>.$}} as the former will check all occurrences of <PA> while the later only check the first match. As the result, CHECK needs putting in all place where <PA> occurs. *) grep <PA> \| count <N> needs a final CHECK-NOT of the same pattern. (As 'CHECK-<N>' is proposed for discussion, converting 'grep \| count <N>' where N > 1 is postponed.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180742 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-29 22:41:29 +00:00			`; RUN: llc < %s -mtriple=x86_64-linux -mcpu=corei7 \| FileCheck %s`
Fix for first part of PR2562. Generate the "pinsrw" instruction for inserts into v4i16 vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53807 91177308-0d34-0410-b5e6-96231b3b80d8 2008-07-20 02:32:23 +00:00			`; PR2562`

Rewrite some tests with FileCHeck in X86 codegen - Revise previous patches of the same purpose by fixing ) grep <PA> \| not grep <PB> semantically is not the same as CHECK: <PA>{{^<PB>.$}} as the former will check all occurrences of <PA> while the later only check the first match. As the result, CHECK needs putting in all place where <PA> occurs. *) grep <PA> \| count <N> needs a final CHECK-NOT of the same pattern. (As 'CHECK-<N>' is proposed for discussion, converting 'grep \| count <N>' where N > 1 is postponed.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180742 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-29 22:41:29 +00:00			`; CHECK: pinsr`

Fix for first part of PR2562. Generate the "pinsrw" instruction for inserts into v4i16 vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53807 91177308-0d34-0410-b5e6-96231b3b80d8 2008-07-20 02:32:23 +00:00			`external global i16 ; <i16*>:0 [#uses=1]`
			`external global <4 x i16> ; <<4 x i16>*>:1 [#uses=2]`

			`declare void @abort()`

			`define void @""() {`
			`load i16* @0 ; <i16>:1 [#uses=1]`
			`load <4 x i16>* @1 ; <<4 x i16>>:2 [#uses=1]`
			`insertelement <4 x i16> %2, i16 %1, i32 0 ; <<4 x i16>>:3 [#uses=1]`
			`store <4 x i16> %3, <4 x i16>* @1`
			`ret void`
			`}`