llvm/test/CodeGen/X86/subreg-to-reg-3.ll

; RUN: llc < %s -march=x86-64 | FileCheck %s

; CHECK: imull

; Don't eliminate or coalesce away the explicit zero-extension!

define i64 @foo(i64 %a) {
  %b = mul i64 %a, 7823
  %c = and i64 %b, 4294967295
  %d = add i64 %c, 1
  ret i64 %d
}
Rewrite some tests with FileCHeck in X86 codegen - Revise previous patches of the same purpose by fixing ) grep <PA> \| not grep <PB> semantically is not the same as CHECK: <PA>{{^<PB>.$}} as the former will check all occurrences of <PA> while the later only check the first match. As the result, CHECK needs putting in all place where <PA> occurs. *) grep <PA> \| count <N> needs a final CHECK-NOT of the same pattern. (As 'CHECK-<N>' is proposed for discussion, converting 'grep \| count <N>' where N > 1 is postponed.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180742 91177308-0d34-0410-b5e6-96231b3b80d8 2013-04-29 22:41:29 +00:00			`; RUN: llc < %s -march=x86-64 \| FileCheck %s`

			`; CHECK: imull`
Implement support for using modeling implicit-zero-extension on x86-64 with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8 2009-04-08 00:15:30 +00:00
			`; Don't eliminate or coalesce away the explicit zero-extension!`

			`define i64 @foo(i64 %a) {`
			`%b = mul i64 %a, 7823`
			`%c = and i64 %b, 4294967295`
			`%d = add i64 %c, 1`
			`ret i64 %d`
			`}`