From 00e3426bc2bc4ae5daa30b0ce8edc2086a1db0cf Mon Sep 17 00:00:00 2001 From: Daniel Cederman Date: Tue, 17 Jul 2018 05:49:33 +0000 Subject: [PATCH] [Sparc] Do not depend on icc for ta 1 The ta instruction will always trap, regardless of the value of the integer condition codes. TRAPri is marked as using icc, so we cannot use a pattern for TRAPri to implement ta 1, as verify-machineinstrs can complain that icc is not defined. Instead we implement ta 1 the same way as ta 5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337236 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Sparc/SparcInstrInfo.td | 4 ++-- test/CodeGen/SPARC/trap.ll | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 9dee18f2563..5b7fb3c485e 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -1009,8 +1009,8 @@ let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [Ha let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>; -def : Pat<(debugtrap), - (TRAPri (i32 G0), (i32 1), (i32 8))>; +let hasSideEffects = 1, rd = 0b01000, rs1 = 0, simm13 = 1 in + def TA1 : F3_2<0b10, 0b111010, (outs), (ins), "ta 1", [(debugtrap)]>; // Section B.28 - Read State Register Instructions let rs2 = 0 in diff --git a/test/CodeGen/SPARC/trap.ll b/test/CodeGen/SPARC/trap.ll index c2f66ca6cbd..12ce8485f0a 100644 --- a/test/CodeGen/SPARC/trap.ll +++ b/test/CodeGen/SPARC/trap.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=sparc-linux-gnu < %s -show-mc-encoding | FileCheck %s +; RUN: llc -mtriple=sparc-linux-gnu < %s -show-mc-encoding -verify-machineinstrs | FileCheck %s define void @test1() { tail call void @llvm.trap()