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Remove isImm(), isReg(), and friends, in favor of

Browse Source 
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-09-13 17:58:21 +00:00
parent b8ca4ff643
commit 014278e6a1
17 changed files with 70 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
include/llvm/CodeGen/MachineOperand.h
View File

@ -139,15 +139,6 @@ public:
bool isGlobalAddress() const { return OpKind == MO_GlobalAddress; }
bool isExternalSymbol() const { return OpKind == MO_ExternalSymbol; }
bool isReg() const { return OpKind == MO_Register; }
bool isImm() const { return OpKind == MO_Immediate; }
bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
bool isFI() const { return OpKind == MO_FrameIndex; }
bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
bool isJTI() const { return OpKind == MO_JumpTableIndex; }
bool isGlobal() const { return OpKind == MO_GlobalAddress; }
bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
//===--------------------------------------------------------------------===//
// Accessors for Register Operands
//===--------------------------------------------------------------------===//
@ -419,7 +410,7 @@ private:
/// or false if not. This can only be called for register operands that are
/// part of a machine instruction.
bool isOnRegUseList() const {
assert(isReg() && "Can only add reg operand to use lists");
assert(isRegister() && "Can only add reg operand to use lists");
return Contents.Reg.Prev != 0;
}

2
lib/CodeGen/BranchFolding.cpp
View File

@ -161,7 +161,7 @@ bool BranchFolder::OptimizeImpDefsBlock(MachineBasicBlock *MBB) {
// See if it uses any of the implicitly defined registers.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i);
if (!MO.isReg() || !MO.isUse())
if (!MO.isRegister() || !MO.isUse())
continue;
unsigned Reg = MO.getReg();
if (ImpDefRegs.count(Reg))

6
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -858,7 +858,7 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li,
unsigned ImpUse = 0;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (MO.isReg()) {
if (MO.isRegister()) {
unsigned Reg = MO.getReg();
if (Reg == 0)
continue;
@ -1592,7 +1592,7 @@ LiveIntervals::handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm,
NewLIs.push_back(&getOrCreateInterval(NewVReg));
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.getReg() == li.reg)
if (MO.isRegister() && MO.getReg() == li.reg)
MO.setReg(NewVReg);
}
}
@ -1636,7 +1636,7 @@ addIntervalsForSpillsFast(const LiveInterval &li,
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& mop = MI->getOperand(i);
if (!mop.isReg() || mop.getReg() != li.reg) continue;
if (!mop.isRegister() || mop.getReg() != li.reg) continue;
HasUse |= MI->getOperand(i).isUse();
HasDef |= MI->getOperand(i).isDef();

3
lib/CodeGen/MachineBasicBlock.cpp
View File

@ -285,7 +285,8 @@ void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
// Scan the operands of this machine instruction, replacing any uses of Old
// with New.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
if (I->getOperand(i).isMBB() && I->getOperand(i).getMBB() == Old)
if (I->getOperand(i).isMachineBasicBlock() &&
I->getOperand(i).getMBB() == Old)
I->getOperand(i).setMBB(New);
}

30
lib/CodeGen/MachineInstr.cpp
View File

@ -37,7 +37,7 @@ using namespace llvm;
/// MachineRegisterInfo. If it is null, then the next/prev fields should be
/// explicitly nulled out.
void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
assert(isReg() && "Can only add reg operand to use lists");
assert(isRegister() && "Can only add reg operand to use lists");
// If the reginfo pointer is null, just explicitly null out or next/prev
// pointers, to ensure they are not garbage.
@ -92,7 +92,7 @@ void MachineOperand::setReg(unsigned Reg) {
void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
// If this operand is currently a register operand, and if this is in a
// function, deregister the operand from the register's use/def list.
if (isReg() && getParent() && getParent()->getParent() &&
if (isRegister() && getParent() && getParent()->getParent() &&
getParent()->getParent()->getParent())
RemoveRegOperandFromRegInfo();
@ -108,7 +108,7 @@ void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
bool isEarlyClobber) {
// If this operand is already a register operand, use setReg to update the
// register's use/def lists.
if (isReg()) {
if (isRegister()) {
setReg(Reg);
} else {
// Otherwise, change this to a register and set the reg#.
@ -354,7 +354,7 @@ MachineInstr::~MachineInstr() {
#ifndef NDEBUG
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
assert((!Operands[i].isRegister() || !Operands[i].isOnRegUseList()) &&
"Reg operand def/use list corrupted");
}
#endif
@ -374,7 +374,7 @@ MachineRegisterInfo *MachineInstr::getRegInfo() {
/// operands already be on their use lists.
void MachineInstr::RemoveRegOperandsFromUseLists() {
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
if (Operands[i].isReg())
if (Operands[i].isRegister())
Operands[i].RemoveRegOperandFromRegInfo();
}
}
@ -384,7 +384,7 @@ void MachineInstr::RemoveRegOperandsFromUseLists() {
/// operands not be on their use lists yet.
void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
if (Operands[i].isReg())
if (Operands[i].isRegister())
Operands[i].AddRegOperandToRegInfo(&RegInfo);
}
}
@ -395,7 +395,7 @@ void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
/// an explicit operand it is added at the end of the explicit operand list
/// (before the first implicit operand).
void MachineInstr::addOperand(const MachineOperand &Op) {
bool isImpReg = Op.isReg() && Op.isImplicit();
bool isImpReg = Op.isRegister() && Op.isImplicit();
assert((isImpReg || !OperandsComplete()) &&
"Trying to add an operand to a machine instr that is already done!");
@ -411,7 +411,7 @@ void MachineInstr::addOperand(const MachineOperand &Op) {
Operands.back().ParentMI = this;
// If the operand is a register, update the operand's use list.
if (Op.isReg())
if (Op.isRegister())
Operands.back().AddRegOperandToRegInfo(getRegInfo());
return;
}
@ -431,7 +431,7 @@ void MachineInstr::addOperand(const MachineOperand &Op) {
// Do explicitly set the reginfo for this operand though, to ensure the
// next/prev fields are properly nulled out.
if (Operands[OpNo].isReg())
if (Operands[OpNo].isRegister())
Operands[OpNo].AddRegOperandToRegInfo(0);
} else if (Operands.size()+1 <= Operands.capacity()) {
@ -444,7 +444,7 @@ void MachineInstr::addOperand(const MachineOperand &Op) {
// list, just remove the implicit operands, add the operand, then re-add all
// the rest of the operands.
for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
assert(Operands[i].isReg() && "Should only be an implicit reg!");
assert(Operands[i].isRegister() && "Should only be an implicit reg!");
Operands[i].RemoveRegOperandFromRegInfo();
}
@ -452,12 +452,12 @@ void MachineInstr::addOperand(const MachineOperand &Op) {
Operands.insert(Operands.begin()+OpNo, Op);
Operands[OpNo].ParentMI = this;
if (Operands[OpNo].isReg())
if (Operands[OpNo].isRegister())
Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
// Re-add all the implicit ops.
for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
assert(Operands[i].isReg() && "Should only be an implicit reg!");
assert(Operands[i].isRegister() && "Should only be an implicit reg!");
Operands[i].AddRegOperandToRegInfo(RegInfo);
}
} else {
@ -483,7 +483,7 @@ void MachineInstr::RemoveOperand(unsigned OpNo) {
// Special case removing the last one.
if (OpNo == Operands.size()-1) {
// If needed, remove from the reg def/use list.
if (Operands.back().isReg() && Operands.back().isOnRegUseList())
if (Operands.back().isRegister() && Operands.back().isOnRegUseList())
Operands.back().RemoveRegOperandFromRegInfo();
Operands.pop_back();
@ -496,7 +496,7 @@ void MachineInstr::RemoveOperand(unsigned OpNo) {
MachineRegisterInfo *RegInfo = getRegInfo();
if (RegInfo) {
for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
if (Operands[i].isReg())
if (Operands[i].isRegister())
Operands[i].RemoveRegOperandFromRegInfo();
}
}
@ -505,7 +505,7 @@ void MachineInstr::RemoveOperand(unsigned OpNo) {
if (RegInfo) {
for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
if (Operands[i].isReg())
if (Operands[i].isRegister())
Operands[i].AddRegOperandToRegInfo(RegInfo);
}
}

2
lib/CodeGen/MachineSink.cpp
View File

@ -155,7 +155,7 @@ bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg()) continue; // Ignore non-register operands.
if (!MO.isRegister()) continue; // Ignore non-register operands.
unsigned Reg = MO.getReg();
if (Reg == 0) continue;

4
lib/CodeGen/RegAllocLocal.cpp
View File

@ -575,7 +575,7 @@ void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
// them for later. Also, we have to process these
// _before_ processing the defs, since an instr
// uses regs before it defs them.
if (MO.isReg() && MO.getReg() && MO.isUse())
if (MO.isRegister() && MO.getReg() && MO.isUse())
LastUseDef[MO.getReg()] = std::make_pair(I, i);
}
@ -584,7 +584,7 @@ void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) {
// Defs others than 2-addr redefs _do_ trigger flag changes:
// - A def followed by a def is dead
// - A use followed by a def is a kill
if (MO.isReg() && MO.getReg() && MO.isDef()) {
if (MO.isRegister() && MO.getReg() && MO.isDef()) {
DenseMap<unsigned, std::pair<MachineInstr*, unsigned> >::iterator
last = LastUseDef.find(MO.getReg());
if (last != LastUseDef.end()) {

4
lib/CodeGen/SimpleRegisterCoalescing.cpp
View File

@ -462,7 +462,7 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
for (unsigned i = CopyMI->getDesc().getNumOperands(),
e = CopyMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = CopyMI->getOperand(i);
if (MO.isReg() && MO.isImplicit())
if (MO.isRegister() && MO.isImplicit())
NewMI->addOperand(MO);
if (MO.isDef() && li_->hasInterval(MO.getReg())) {
unsigned Reg = MO.getReg();
@ -867,7 +867,7 @@ void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li,
// Each use MI may have multiple uses of this register. Change them all.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.getReg() == li.reg)
if (MO.isRegister() && MO.getReg() == li.reg)
MO.setReg(DstReg);
}
JoinedCopies.insert(MI);

6
lib/CodeGen/TargetInstrInfoImpl.cpp
View File

@ -87,13 +87,13 @@ bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
if (TID.OpInfo[i].isPredicate()) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isReg()) {
if (MO.isRegister()) {
MO.setReg(Pred[j].getReg());
MadeChange = true;
} else if (MO.isImm()) {
} else if (MO.isImmediate()) {
MO.setImm(Pred[j].getImm());
MadeChange = true;
} else if (MO.isMBB()) {
} else if (MO.isMachineBasicBlock()) {
MO.setMBB(Pred[j].getMBB());
MadeChange = true;
}

2
lib/CodeGen/UnreachableBlockElim.cpp
View File

@ -127,7 +127,7 @@ bool UnreachableMachineBlockElim::runOnMachineFunction(MachineFunction &F) {
while (start != succ->end() &&
start->getOpcode() == TargetInstrInfo::PHI) {
for (unsigned i = start->getNumOperands() - 1; i >= 2; i-=2)
if (start->getOperand(i).isMBB() &&
if (start->getOperand(i).isMachineBasicBlock() &&
start->getOperand(i).getMBB() == BB) {
start->RemoveOperand(i);
start->RemoveOperand(i-1);

2
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -1058,7 +1058,7 @@ bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &Fn,
// Finally, change the CPI in the instruction operand to be ID.
for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
if (UserMI->getOperand(i).isCPI()) {
if (UserMI->getOperand(i).isConstantPoolIndex()) {
UserMI->getOperand(i).setIndex(ID);
break;
}

8
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -106,8 +106,8 @@ unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
case PPC::LWZ:
case PPC::LFS:
case PPC::LFD:
if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFI()) {
if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getIndex();
return MI->getOperand(0).getReg();
}
@ -124,8 +124,8 @@ unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
case PPC::STW:
case PPC::STFS:
case PPC::STFD:
if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFI()) {
if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getIndex();
return MI->getOperand(0).getReg();
}

4
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -1368,7 +1368,7 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
} else if (RetOpcode == PPC::TCRETURNri) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
assert(JumpTarget.isReg() && "Expecting register operand.");
assert(JumpTarget.isRegister() && "Expecting register operand.");
BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR));
} else if (RetOpcode == PPC::TCRETURNai) {
MBBI = prior(MBB.end());
@ -1382,7 +1382,7 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
} else if (RetOpcode == PPC::TCRETURNri8) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
assert(JumpTarget.isReg() && "Expecting register operand.");
assert(JumpTarget.isRegister() && "Expecting register operand.");
BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR8));
} else if (RetOpcode == PPC::TCRETURNai8) {
MBBI = prior(MBB.end());

8
lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -173,7 +173,7 @@ void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
else if (MO.isImmediate())
MIB.addImm(MO.getImm());
else {
assert(MO.isFI());
assert(MO.isFrameIndex());
MIB.addFrameIndex(MO.getIndex());
}
}
@ -212,12 +212,12 @@ void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isReg())
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImm())
else if (MO.isImmediate())
MIB.addImm(MO.getImm());
else {
assert(MO.isFI());
assert(MO.isFrameIndex());
MIB.addFrameIndex(MO.getIndex());
}
}

4
lib/Target/X86/X86FloatingPoint.cpp
View File

@ -1015,7 +1015,7 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
unsigned NumKills = 0;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &Op = MI->getOperand(i);
if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
if (!Op.isRegister() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
continue;
assert(Op.isUse() && "Only handle inline asm uses right now");
@ -1055,7 +1055,7 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &Op = MI->getOperand(i);
if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
if (!Op.isRegister() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
continue;
// FP Register uses must be kills unless there are two uses of the same
// register, in which case only one will be a kill.

14
lib/Target/X86/X86ISelLowering.cpp
View File

@ -6273,9 +6273,10 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
tt = t1;
unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
&& "invalid operand");
if (argOpers[valArgIndx]->isReg())
assert((argOpers[valArgIndx]->isRegister() ||
argOpers[valArgIndx]->isImmediate()) &&
"invalid operand");
if (argOpers[valArgIndx]->isRegister())
MIB = BuildMI(newMBB, TII->get(regOpc), t2);
else
MIB = BuildMI(newMBB, TII->get(immOpc), t2);
@ -6360,11 +6361,12 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
(*MIB).addOperand(*argOpers[i]);
// We only support register and immediate values
assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
&& "invalid operand");
assert((argOpers[valArgIndx]->isRegister() ||
argOpers[valArgIndx]->isImmediate()) &&
"invalid operand");
unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
if (argOpers[valArgIndx]->isReg())
if (argOpers[valArgIndx]->isRegister())
MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
else
MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);

36
lib/Target/X86/X86InstrInfo.cpp
View File

@ -705,8 +705,8 @@ unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
case X86::MOVAPDrm:
case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm:
if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0 &&
MI->getOperand(4).getImm() == 0) {
@ -736,8 +736,8 @@ unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
case X86::MMX_MOVD64mr:
case X86::MMX_MOVQ64mr:
case X86::MMX_MOVNTQmr:
if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
MI->getOperand(1).getImm() == 1 &&
MI->getOperand(2).getReg() == 0 &&
MI->getOperand(3).getImm() == 0) {
@ -789,17 +789,17 @@ X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm: {
// Loads from constant pools are trivially rematerializable.
if (MI->getOperand(1).isReg() &&
MI->getOperand(2).isImm() &&
MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
(MI->getOperand(4).isCPI() ||
(MI->getOperand(4).isGlobal() &&
if (MI->getOperand(1).isRegister() &&
MI->getOperand(2).isImmediate() &&
MI->getOperand(3).isRegister() && MI->getOperand(3).getReg() == 0 &&
(MI->getOperand(4).isConstantPoolIndex() ||
(MI->getOperand(4).isGlobalAddress() &&
isGVStub(MI->getOperand(4).getGlobal(), TM)))) {
unsigned BaseReg = MI->getOperand(1).getReg();
if (BaseReg == 0)
return true;
// Allow re-materialization of PIC load.
if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
if (!ReMatPICStubLoad && MI->getOperand(4).isGlobalAddress())
return false;
const MachineFunction &MF = *MI->getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
@ -819,10 +819,10 @@ X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
case X86::LEA32r:
case X86::LEA64r: {
if (MI->getOperand(1).isReg() &&
MI->getOperand(2).isImm() &&
MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
!MI->getOperand(4).isReg()) {
if (MI->getOperand(1).isRegister() &&
MI->getOperand(2).isImmediate() &&
MI->getOperand(3).isRegister() && MI->getOperand(3).getReg() == 0 &&
!MI->getOperand(4).isRegister()) {
// lea fi#, lea GV, etc. are all rematerializable.
unsigned BaseReg = MI->getOperand(1).getReg();
if (BaseReg == 0)
@ -879,7 +879,7 @@ void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
const MachineInstr *Orig) const {
unsigned SubIdx = Orig->getOperand(0).isReg()
unsigned SubIdx = Orig->getOperand(0).isRegister()
? Orig->getOperand(0).getSubReg() : 0;
bool ChangeSubIdx = SubIdx != 0;
if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
@ -941,14 +941,14 @@ bool X86InstrInfo::isInvariantLoad(MachineInstr *MI) const {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
// Loads from constant pools are trivially invariant.
if (MO.isCPI())
if (MO.isConstantPoolIndex())
return true;
if (MO.isGlobal())
if (MO.isGlobalAddress())
return isGVStub(MO.getGlobal(), TM);
// If this is a load from an invariant stack slot, the load is a constant.
if (MO.isFI()) {
if (MO.isFrameIndex()) {
const MachineFrameInfo &MFI =
*MI->getParent()->getParent()->getFrameInfo();
int Idx = MO.getIndex();