From 01765eb0a187c103b21c265c60b45ecd2b538852 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Thu, 12 May 2011 17:42:08 +0000 Subject: [PATCH] Fix setting of isCommutable flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131233 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsInstrFPU.td | 8 +++++--- lib/Target/Mips/MipsInstrInfo.td | 33 +++++++++++++++++++------------- 2 files changed, 25 insertions(+), 16 deletions(-) diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 576bec0dddd..72ed3e6700f 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -100,7 +100,8 @@ class FFR1_3 funct, bits<5> fmt, RegisterClass RcSrc, !strconcat(asmstr, " $fd, $fs"), []>; -multiclass FFR1_4 funct, string asmstr, SDNode FOp> { +multiclass FFR1_4 funct, string asmstr, SDNode FOp, bit isComm = 0> { + let isCommutable = isComm in { def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs, FGR32:$ft), !strconcat(asmstr, ".s $fd, $fs, $ft"), @@ -111,6 +112,7 @@ multiclass FFR1_4 funct, string asmstr, SDNode FOp> { !strconcat(asmstr, ".d $fd, $fs, $ft"), [(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>, Requires<[In32BitMode]>; + } } //===----------------------------------------------------------------------===// @@ -203,9 +205,9 @@ def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr), "swc1 $ft, $addr", [(store FGR32:$ft, addr:$addr)]>; /// Floating-point Aritmetic -defm FADD : FFR1_4<0x10, "add", fadd>; +defm FADD : FFR1_4<0x10, "add", fadd, 1>; defm FDIV : FFR1_4<0x03, "div", fdiv>; -defm FMUL : FFR1_4<0x02, "mul", fmul>; +defm FMUL : FFR1_4<0x02, "mul", fmul, 1>; defm FSUB : FFR1_4<0x01, "sub", fsub>; //===----------------------------------------------------------------------===// diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 472373af881..07be0ac6976 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -145,17 +145,19 @@ def addr : ComplexPattern; //===----------------------------------------------------------------------===// // Arithmetic 3 register operands -let isCommutable = 1 in class ArithR op, bits<6> func, string instr_asm, SDNode OpNode, - InstrItinClass itin>: + InstrItinClass itin, bit isComm = 0>: FR; + [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin> { + let isCommutable = isComm; +} -let isCommutable = 1 in -class ArithOverflowR op, bits<6> func, string instr_asm>: +class ArithOverflowR op, bits<6> func, string instr_asm, bit isComm = 0>: FR; + !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu> { + let isCommutable = isComm; +} // Arithmetic 2 register operands class ArithI op, string instr_asm, SDNode OpNode, @@ -171,12 +173,15 @@ class ArithOverflowI op, string instr_asm, SDNode OpNode, // Arithmetic Multiply ADD/SUB let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in -class MArithR func, string instr_asm, SDNode op> : +class MArithR func, string instr_asm, SDNode op, bit isComm = 0> : FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), !strconcat(instr_asm, "\t$rs, $rt"), - [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul>; + [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { + let isCommutable = isComm; +} // Logical +let isCommutable = 1 in class LogicR func, string instr_asm, SDNode OpNode>: FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c), !strconcat(instr_asm, "\t$dst, $b, $c"), @@ -187,6 +192,7 @@ class LogicI op, string instr_asm, SDNode OpNode>: !strconcat(instr_asm, "\t$dst, $b, $c"), [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>; +let isCommutable = 1 in class LogicNOR op, bits<6> func, string instr_asm>: FR func, string instr_asm, InstrItinClass itin>: FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b), !strconcat(instr_asm, "\t$a, $b"), [], itin>; @@ -394,9 +401,9 @@ def XORi : LogicI<0x0e, "xori", xor>; def LUi : LoadUpper<0x0f, "lui">; /// Arithmetic Instructions (3-Operand, R-Type) -def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>; +def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu, 1>; def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>; -def ADD : ArithOverflowR<0x00, 0x20, "add">; +def ADD : ArithOverflowR<0x00, 0x20, "add", 1>; def SUB : ArithOverflowR<0x00, 0x22, "sub">; def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>; def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>; @@ -520,14 +527,14 @@ let addr=0 in def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">; // MADD*/MSUB* -def MADD : MArithR<0, "madd", MipsMAdd>; -def MADDU : MArithR<1, "maddu", MipsMAddu>; +def MADD : MArithR<0, "madd", MipsMAdd, 1>; +def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; def MSUB : MArithR<4, "msub", MipsMSub>; def MSUBU : MArithR<5, "msubu", MipsMSubu>; // MUL is a assembly macro in the current used ISAs. In recent ISA's // it is a real instruction. -def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>, Requires<[IsMips32]>; +def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul, 1>, Requires<[IsMips32]>; //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions