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ARM: provide diagnostics on more writeback LDM/STM instructions
The set of circumstances where the writeback register is allowed to be in the list of registers is rather baroque, but I think this implements them all on the assembly parsing side. For disassembly, we still warn about an ARM-mode LDM even if the architecture revision is < v7 (the required architecture information isn't available). It's a silly instruction anyway, so hopefully no-one will mind. rdar://problem/15223374 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193185 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
parent
e18273b7be
commit
01b0e94bb7
@ -5416,6 +5416,7 @@ validateInstruction(MCInst &Inst,
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"bitfield width must be in range [1,32-lsb]");
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return false;
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}
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// Notionally handles ARM::tLDMIA_UPD too.
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case ARM::tLDMIA: {
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// If we're parsing Thumb2, the .w variant is available and handles
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// most cases that are normally illegal for a Thumb1 LDM instruction.
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@ -5444,7 +5445,19 @@ validateInstruction(MCInst &Inst,
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break;
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}
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case ARM::t2LDMIA_UPD: {
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case ARM::LDMIA_UPD:
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case ARM::LDMDB_UPD:
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case ARM::LDMIB_UPD:
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case ARM::LDMDA_UPD:
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// ARM variants loading and updating the same register are only officially
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// UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
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if (!hasV7Ops())
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break;
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// Fallthrough
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case ARM::t2LDMIA_UPD:
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case ARM::t2LDMDB_UPD:
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case ARM::t2STMIA_UPD:
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case ARM::t2STMDB_UPD: {
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if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
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return Error(Operands[4]->getStartLoc(),
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"writeback operator '!' not allowed when base register "
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@ -5490,10 +5503,19 @@ validateInstruction(MCInst &Inst,
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break;
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}
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case ARM::tSTMIA_UPD: {
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bool ListContainsBase;
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if (checkLowRegisterList(Inst, 4, 0, 0, ListContainsBase) && !isThumbTwo())
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bool ListContainsBase, InvalidLowList;
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InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
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0, ListContainsBase);
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if (InvalidLowList && !isThumbTwo())
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return Error(Operands[4]->getStartLoc(),
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"registers must be in range r0-r7");
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// This would be converted to a 32-bit stm, but that's not valid if the
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// writeback register is in the list.
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if (InvalidLowList && ListContainsBase)
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return Error(Operands[4]->getStartLoc(),
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"writeback operator '!' not allowed when base register "
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"in register list");
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break;
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}
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case ARM::tADDrSP: {
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@ -1203,20 +1203,22 @@ static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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bool writebackLoad = false;
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unsigned writebackReg = 0;
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bool NeedDisjointWriteback = false;
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unsigned WritebackReg = 0;
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switch (Inst.getOpcode()) {
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default:
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break;
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case ARM::LDMIA_UPD:
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case ARM::LDMDB_UPD:
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case ARM::LDMIB_UPD:
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case ARM::LDMDA_UPD:
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case ARM::t2LDMIA_UPD:
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case ARM::t2LDMDB_UPD:
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writebackLoad = true;
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writebackReg = Inst.getOperand(0).getReg();
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break;
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default:
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break;
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case ARM::LDMIA_UPD:
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case ARM::LDMDB_UPD:
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case ARM::LDMIB_UPD:
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case ARM::LDMDA_UPD:
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case ARM::t2LDMIA_UPD:
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case ARM::t2LDMDB_UPD:
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case ARM::t2STMIA_UPD:
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case ARM::t2STMDB_UPD:
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NeedDisjointWriteback = true;
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WritebackReg = Inst.getOperand(0).getReg();
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break;
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}
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// Empty register lists are not allowed.
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@ -1226,7 +1228,7 @@ static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
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if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
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return MCDisassembler::Fail;
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// Writeback not allowed if Rn is in the target list.
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if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
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if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
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Check(S, MCDisassembler::SoftFail);
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}
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}
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@ -429,3 +429,10 @@
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bkpteq #7
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@ CHECK-ERRORS: error: instruction 'bkpt' is not predicable, but condition code specified
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ldm r2!, {r2, r3}
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ldmdb r2!, {r2, r3}
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ldmda r2!, {r2, r3}
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@ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
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@ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
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@ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
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@ -57,6 +57,8 @@ error: invalid operand for instruction
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ldm r2!, {r5, r8}
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ldm r2, {r5, r7}
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ldm r2!, {r2, r3, r4}
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ldm r2!, {r2, r3, r4, r10}
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ldmdb r2!, {r2, r3, r4}
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@ CHECK-ERRORS: error: registers must be in range r0-r7
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@ CHECK-ERRORS: ldm r2!, {r5, r8}
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@ CHECK-ERRORS: ^
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@ -66,6 +68,12 @@ error: invalid operand for instruction
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@ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
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@ CHECK-ERRORS: ldm r2!, {r2, r3, r4}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
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@ CHECK-ERRORS-V8: ldm r2!, {r2, r3, r4, r10}
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@ CHECK-ERRORS-V8: ^
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@ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
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@ CHECK-ERRORS-V8: ldmdb r2!, {r2, r3, r4}
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@ CHECK-ERRORS-V8: ^
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@ Invalid writeback and register lists for PUSH/POP
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pop {r1, r2, r10}
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@ -81,12 +89,20 @@ error: invalid operand for instruction
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@ Invalid writeback and register lists for STM
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stm r1, {r2, r6}
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stm r1!, {r2, r9}
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stm r2!, {r2, r9}
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stmdb r2!, {r0, r2}
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: stm r1, {r2, r6}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: registers must be in range r0-r7
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@ CHECK-ERRORS: stm r1!, {r2, r9}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
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@ CHECK-ERRORS-V8: stm r2!, {r2, r9}
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@ CHECK-ERRORS-V8: ^
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@ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
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@ CHECK-ERRORS-V8: stmdb r2!, {r0, r2}
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@ CHECK-ERRORS-V8: ^
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@ Out of range immediates for LSL instruction.
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lsls r4, r5, #-1
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@ -389,3 +389,19 @@
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[0x80 0xf9 0x30 0x0b]
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# CHECK: invalid instruction encoding
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# CHECK-NEXT: [0x80 0xf9 0x30 0x0b]
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#------------------------------------------------------------------------------
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# Unpredictable STMs
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#------------------------------------------------------------------------------
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# 32-bit Thumb STM instructions cannot have a writeback register which appears
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# in the list.
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[0xa1,0xe8,0x07,0x04]
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# CHECK: warning: potentially undefined instruction encoding
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# CHECK-NEXT: [0xa1,0xe8,0x07,0x04]
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[0x21,0xe9,0x07,0x04]
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# CHECK: warning: potentially undefined instruction encoding
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# CHECK-NEXT: [0x21,0xe9,0x07,0x04]
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