diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 060b36c868e..f2c5040b89e 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -18060,7 +18060,7 @@ static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
   // TODO: If we had general constant folding for FP logic ops, this check
   // wouldn't be necessary.
   SDValue MagBits;
-  if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Mag)) {
+  if (ConstantFPSDNode *Op0CN = isConstOrConstSplatFP(Mag)) {
     APFloat APF = Op0CN->getValueAPF();
     APF.clearSign();
     MagBits = DAG.getConstantFP(APF, dl, LogicVT);
diff --git a/test/CodeGen/X86/sse1-fcopysign.ll b/test/CodeGen/X86/sse1-fcopysign.ll
index 59598ecd5df..ed7f31e444c 100644
--- a/test/CodeGen/X86/sse1-fcopysign.ll
+++ b/test/CodeGen/X86/sse1-fcopysign.ll
@@ -71,18 +71,16 @@ define <4 x float> @v4f32_neg(<4 x float> %a, <4 x float> %b) nounwind {
 define <4 x float> @v4f32_const_mag(<4 x float> %a, <4 x float> %b) nounwind {
 ; X86-LABEL: v4f32_const_mag:
 ; X86:       # %bb.0:
-; X86-NEXT:    andps {{\.LCPI.*}}, %xmm1
-; X86-NEXT:    movaps {{.*#+}} xmm0 = [1,1,1,1]
+; X86-NEXT:    movaps %xmm1, %xmm0
 ; X86-NEXT:    andps {{\.LCPI.*}}, %xmm0
-; X86-NEXT:    orps %xmm1, %xmm0
+; X86-NEXT:    orps {{\.LCPI.*}}, %xmm0
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: v4f32_const_mag:
 ; X64:       # %bb.0:
-; X64-NEXT:    andps {{.*}}(%rip), %xmm1
-; X64-NEXT:    movaps {{.*#+}} xmm0 = [1,1,1,1]
+; X64-NEXT:    movaps %xmm1, %xmm0
 ; X64-NEXT:    andps {{.*}}(%rip), %xmm0
-; X64-NEXT:    orps %xmm1, %xmm0
+; X64-NEXT:    orps {{.*}}(%rip), %xmm0
 ; X64-NEXT:    retq
   %tmp = tail call <4 x float> @llvm.copysign.v4f32(<4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> %b )
   ret <4 x float> %tmp