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Fix some shift bugs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21126 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2779,8 +2779,13 @@ void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
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.addImm(32-Amount).addImm(Amount).addImm(31);
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BuildMI(*MBB, IP, PPC::RLWIMI, 5, DestReg+1).addReg(TempReg)
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.addReg(SrcReg).addImm(32-Amount).addImm(0).addImm(Amount-1);
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BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
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.addImm(32-Amount).addImm(Amount).addImm(31);
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if (isSigned) {
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BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg)
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.addImm(Amount);
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} else {
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BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
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.addImm(32-Amount).addImm(Amount).addImm(31);
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}
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}
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} else { // Shifting more than 32 bits
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Amount -= 32;
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@ -2805,7 +2810,11 @@ void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
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BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
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.addReg(SrcReg);
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}
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BuildMI(*MBB, IP,PPC::LI, 1, DestReg).addSImm(0);
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if (isSigned)
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BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg)
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.addImm(31);
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else
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BuildMI(*MBB, IP,PPC::LI, 1, DestReg).addSImm(0);
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}
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}
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} else {
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