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[AVX-512] Fix some patterns to use extended register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290536 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
a7c4539a02
commit
02926157aa
@ -3001,24 +3001,24 @@ def : Pat<(v16i32 (vselect (xor VK16:$mask, (v16i1 immAllOnesV)),
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let Predicates = [HasVLX, NoBWI] in {
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// 128-bit load/store without BWI.
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def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
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(VMOVDQA32Z128mr addr:$dst, VR128:$src)>;
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def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
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(VMOVDQA32Z128mr addr:$dst, VR128:$src)>;
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def : Pat<(store (v8i16 VR128:$src), addr:$dst),
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(VMOVDQU32Z128mr addr:$dst, VR128:$src)>;
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def : Pat<(store (v16i8 VR128:$src), addr:$dst),
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(VMOVDQU32Z128mr addr:$dst, VR128:$src)>;
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def : Pat<(alignedstore (v8i16 VR128X:$src), addr:$dst),
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(VMOVDQA32Z128mr addr:$dst, VR128X:$src)>;
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def : Pat<(alignedstore (v16i8 VR128X:$src), addr:$dst),
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(VMOVDQA32Z128mr addr:$dst, VR128X:$src)>;
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def : Pat<(store (v8i16 VR128X:$src), addr:$dst),
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(VMOVDQU32Z128mr addr:$dst, VR128X:$src)>;
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def : Pat<(store (v16i8 VR128X:$src), addr:$dst),
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(VMOVDQU32Z128mr addr:$dst, VR128X:$src)>;
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// 256-bit load/store without BWI.
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def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
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(VMOVDQA32Z256mr addr:$dst, VR256:$src)>;
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def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
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(VMOVDQA32Z256mr addr:$dst, VR256:$src)>;
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def : Pat<(store (v16i16 VR256:$src), addr:$dst),
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(VMOVDQU32Z256mr addr:$dst, VR256:$src)>;
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def : Pat<(store (v32i8 VR256:$src), addr:$dst),
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(VMOVDQU32Z256mr addr:$dst, VR256:$src)>;
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def : Pat<(alignedstore256 (v16i16 VR256X:$src), addr:$dst),
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(VMOVDQA32Z256mr addr:$dst, VR256X:$src)>;
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def : Pat<(alignedstore256 (v32i8 VR256X:$src), addr:$dst),
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(VMOVDQA32Z256mr addr:$dst, VR256X:$src)>;
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def : Pat<(store (v16i16 VR256X:$src), addr:$dst),
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(VMOVDQU32Z256mr addr:$dst, VR256X:$src)>;
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def : Pat<(store (v32i8 VR256X:$src), addr:$dst),
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(VMOVDQU32Z256mr addr:$dst, VR256X:$src)>;
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}
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let Predicates = [HasVLX] in {
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@ -6618,16 +6618,16 @@ let Predicates = [HasAVX512, HasVLX] in {
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let AddedComplexity = 15 in {
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def : Pat<(X86vzmovl (v2i64 (bitconvert
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(v4i32 (X86cvtp2Int (v2f64 VR128X:$src)))))),
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(VCVTPD2DQZ128rr VR128:$src)>;
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(VCVTPD2DQZ128rr VR128X:$src)>;
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def : Pat<(v4i32 (bitconvert (X86vzmovl (v2i64 (bitconvert
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(v4i32 (X86cvtp2UInt (v2f64 VR128X:$src)))))))),
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(VCVTPD2UDQZ128rr VR128:$src)>;
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(VCVTPD2UDQZ128rr VR128X:$src)>;
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def : Pat<(X86vzmovl (v2i64 (bitconvert
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(v4i32 (X86cvttp2si (v2f64 VR128X:$src)))))),
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(VCVTTPD2DQZ128rr VR128:$src)>;
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(VCVTTPD2DQZ128rr VR128X:$src)>;
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def : Pat<(v4i32 (bitconvert (X86vzmovl (v2i64 (bitconvert
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(v4i32 (X86cvttp2ui (v2f64 VR128X:$src)))))))),
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(VCVTTPD2UDQZ128rr VR128:$src)>;
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(VCVTTPD2UDQZ128rr VR128X:$src)>;
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}
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}
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@ -6642,10 +6642,10 @@ let Predicates = [HasDQI, HasVLX] in {
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let AddedComplexity = 15 in {
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def : Pat<(X86vzmovl (v2f64 (bitconvert
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(v4f32 (X86VSintToFP (v2i64 VR128X:$src)))))),
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(VCVTQQ2PSZ128rr VR128:$src)>;
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(VCVTQQ2PSZ128rr VR128X:$src)>;
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def : Pat<(X86vzmovl (v2f64 (bitconvert
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(v4f32 (X86VUintToFP (v2i64 VR128X:$src)))))),
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(VCVTUQQ2PSZ128rr VR128:$src)>;
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(VCVTUQQ2PSZ128rr VR128X:$src)>;
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}
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}
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@ -8552,33 +8552,42 @@ multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
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defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
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def avx512_v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
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VR128X:$src))>;
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def avx512_v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128X:$src, (i8 15)))>;
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def avx512_v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128X:$src, (i8 31)))>;
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def avx512_v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
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VR256X:$src))>;
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def avx512_v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256X:$src, (i8 15)))>;
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def avx512_v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256X:$src, (i8 31)))>;
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let Predicates = [HasBWI, HasVLX] in {
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def : Pat<(xor
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(bc_v2i64 (v16i1sextv16i8)),
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(bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
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(VPABSBZ128rr VR128:$src)>;
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(bc_v2i64 (avx512_v16i1sextv16i8)),
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(bc_v2i64 (add (v16i8 VR128X:$src), (avx512_v16i1sextv16i8)))),
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(VPABSBZ128rr VR128X:$src)>;
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def : Pat<(xor
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(bc_v2i64 (v8i1sextv8i16)),
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(bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
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(VPABSWZ128rr VR128:$src)>;
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(bc_v2i64 (avx512_v8i1sextv8i16)),
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(bc_v2i64 (add (v8i16 VR128X:$src), (avx512_v8i1sextv8i16)))),
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(VPABSWZ128rr VR128X:$src)>;
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def : Pat<(xor
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(bc_v4i64 (v32i1sextv32i8)),
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(bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
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(VPABSBZ256rr VR256:$src)>;
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(bc_v4i64 (avx512_v32i1sextv32i8)),
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(bc_v4i64 (add (v32i8 VR256X:$src), (avx512_v32i1sextv32i8)))),
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(VPABSBZ256rr VR256X:$src)>;
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def : Pat<(xor
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(bc_v4i64 (v16i1sextv16i16)),
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(bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
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(VPABSWZ256rr VR256:$src)>;
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(bc_v4i64 (avx512_v16i1sextv16i16)),
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(bc_v4i64 (add (v16i16 VR256X:$src), (avx512_v16i1sextv16i16)))),
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(VPABSWZ256rr VR256X:$src)>;
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}
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let Predicates = [HasAVX512, HasVLX] in {
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def : Pat<(xor
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(bc_v2i64 (v4i1sextv4i32)),
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(bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
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(VPABSDZ128rr VR128:$src)>;
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(bc_v2i64 (avx512_v4i1sextv4i32)),
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(bc_v2i64 (add (v4i32 VR128X:$src), (avx512_v4i1sextv4i32)))),
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(VPABSDZ128rr VR128X:$src)>;
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def : Pat<(xor
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(bc_v4i64 (v8i1sextv8i32)),
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(bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
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(VPABSDZ256rr VR256:$src)>;
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(bc_v4i64 (avx512_v8i1sextv8i32)),
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(bc_v4i64 (add (v8i32 VR256X:$src), (avx512_v8i1sextv8i32)))),
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(VPABSDZ256rr VR256X:$src)>;
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}
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let Predicates = [HasAVX512] in {
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@ -9086,27 +9095,27 @@ defm VFIXUPIMMPD : avx512_fixupimm_packed_all<avx512vl_f64_info>,
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multiclass AVX512_scalar_math_f32_patterns<SDNode Op, string OpcPrefix> {
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let Predicates = [HasAVX512] in {
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// extracted scalar math op with insert via movss
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def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
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(Op (f32 (extractelt (v4f32 VR128:$dst), (iPTR 0))),
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FR32:$src))))),
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def : Pat<(v4f32 (X86Movss (v4f32 VR128X:$dst), (v4f32 (scalar_to_vector
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(Op (f32 (extractelt (v4f32 VR128X:$dst), (iPTR 0))),
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FR32X:$src))))),
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(!cast<I>("V"#OpcPrefix#SSZrr_Int) v4f32:$dst,
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(COPY_TO_REGCLASS FR32:$src, VR128))>;
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(COPY_TO_REGCLASS FR32X:$src, VR128X))>;
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// extracted scalar math op with insert via blend
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def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
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(Op (f32 (extractelt (v4f32 VR128:$dst), (iPTR 0))),
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FR32:$src))), (i8 1))),
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def : Pat<(v4f32 (X86Blendi (v4f32 VR128X:$dst), (v4f32 (scalar_to_vector
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(Op (f32 (extractelt (v4f32 VR128X:$dst), (iPTR 0))),
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FR32X:$src))), (i8 1))),
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(!cast<I>("V"#OpcPrefix#SSZrr_Int) v4f32:$dst,
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(COPY_TO_REGCLASS FR32:$src, VR128))>;
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(COPY_TO_REGCLASS FR32X:$src, VR128X))>;
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// vector math op with insert via movss
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def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
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(Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
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def : Pat<(v4f32 (X86Movss (v4f32 VR128X:$dst),
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(Op (v4f32 VR128X:$dst), (v4f32 VR128X:$src)))),
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(!cast<I>("V"#OpcPrefix#SSZrr_Int) v4f32:$dst, v4f32:$src)>;
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// vector math op with insert via blend
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def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
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(Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
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def : Pat<(v4f32 (X86Blendi (v4f32 VR128X:$dst),
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(Op (v4f32 VR128X:$dst), (v4f32 VR128X:$src)), (i8 1))),
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(!cast<I>("V"#OpcPrefix#SSZrr_Int) v4f32:$dst, v4f32:$src)>;
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}
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}
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@ -9119,27 +9128,27 @@ defm : AVX512_scalar_math_f32_patterns<fdiv, "DIV">;
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multiclass AVX512_scalar_math_f64_patterns<SDNode Op, string OpcPrefix> {
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let Predicates = [HasAVX512] in {
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// extracted scalar math op with insert via movsd
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def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
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(Op (f64 (extractelt (v2f64 VR128:$dst), (iPTR 0))),
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FR64:$src))))),
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def : Pat<(v2f64 (X86Movsd (v2f64 VR128X:$dst), (v2f64 (scalar_to_vector
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(Op (f64 (extractelt (v2f64 VR128X:$dst), (iPTR 0))),
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FR64X:$src))))),
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(!cast<I>("V"#OpcPrefix#SDZrr_Int) v2f64:$dst,
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(COPY_TO_REGCLASS FR64:$src, VR128))>;
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(COPY_TO_REGCLASS FR64X:$src, VR128X))>;
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// extracted scalar math op with insert via blend
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def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
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(Op (f64 (extractelt (v2f64 VR128:$dst), (iPTR 0))),
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FR64:$src))), (i8 1))),
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def : Pat<(v2f64 (X86Blendi (v2f64 VR128X:$dst), (v2f64 (scalar_to_vector
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(Op (f64 (extractelt (v2f64 VR128X:$dst), (iPTR 0))),
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FR64X:$src))), (i8 1))),
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(!cast<I>("V"#OpcPrefix#SDZrr_Int) v2f64:$dst,
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(COPY_TO_REGCLASS FR64:$src, VR128))>;
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(COPY_TO_REGCLASS FR64X:$src, VR128X))>;
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// vector math op with insert via movsd
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def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
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(Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
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def : Pat<(v2f64 (X86Movsd (v2f64 VR128X:$dst),
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(Op (v2f64 VR128X:$dst), (v2f64 VR128X:$src)))),
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(!cast<I>("V"#OpcPrefix#SDZrr_Int) v2f64:$dst, v2f64:$src)>;
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// vector math op with insert via blend
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def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
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(Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
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def : Pat<(v2f64 (X86Blendi (v2f64 VR128X:$dst),
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(Op (v2f64 VR128X:$dst), (v2f64 VR128X:$src)), (i8 1))),
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(!cast<I>("V"#OpcPrefix#SDZrr_Int) v2f64:$dst, v2f64:$src)>;
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}
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}
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