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ARM: workaround bundled operation predication

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This is a Windows ARM specific issue.  If the code path in the if conversion
ends up using a relocation which will form a IMAGE_REL_ARM_MOV32T, we end up
with a bundle to ensure that the mov.w/mov.t pair is not split up.  This is
normally fine, however, if the branch is also predicated, then we end up trying
to predicate the bundle.

For now, report a bundle as being unpredicatable.  Although this is false, this
would trigger a failure case previously anyways, so this is no worse.  That is,
there should not be any code which would previously have been if converted and
predicated which would not be now.

Under certain circumstances, it may be possible to "predicate the bundle".  This
would require scanning all bundle instructions, and ensure that the bundle
contains only predicatable instructions, and converting the bundle into an IT
block sequence.  If the bundle is larger than the maximal IT block length (4
instructions), it would require materializing multiple IT blocks from the single
bundle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280689 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Saleem Abdulrasool 2016-09-06 04:00:12 +00:00
parent c581dfbe75
commit 02c3a66ad9
2 changed files with 27 additions and 0 deletions
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3
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -575,6 +575,9 @@ bool ARMBaseInstrInfo::isPredicable(MachineInstr &MI) const {
if (!MI.isPredicable())
return false;
if (MI.isBundle())
return false;
if (!isEligibleForITBlock(&MI))
return false;

24
test/CodeGen/ARM/Windows/if-cvt-bundle.ll Normal file
View File

@ -0,0 +1,24 @@
; RUN: llc -mtriple thumbv7--windows-itanium -filetype asm -o - %s | FileCheck %s
declare void @llvm.trap()
declare arm_aapcs_vfpcc zeroext i1 @g()
define arm_aapcs_vfpcc i8* @f() {
entry:
%call = tail call arm_aapcs_vfpcc zeroext i1 @g()
br i1 %call, label %if.then, label %if.end
if.then:
ret i8* bitcast (i1 ()* @g to i8*)
if.end:
tail call void @llvm.trap()
unreachable
}
; CHECK: push.w {r11, lr}
; CHECK: bl g
; CHECK: movw [[REG:r[0-9]+]], :lower16:g
; CHECK: movt [[REG]], :upper16:g
; CHECK: pop.w {r11, pc}