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Add CLAC/STAC instruction encoding/decoding support
As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
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Michael Liao
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959ddbb5e0
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02d2e61252
@ -274,11 +274,12 @@ namespace X86II {
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//// MRM_XX - A mod/rm byte of exactly 0xXX.
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MRM_C1 = 33, MRM_C2 = 34, MRM_C3 = 35, MRM_C4 = 36,
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MRM_C8 = 37, MRM_C9 = 38, MRM_E8 = 39, MRM_F0 = 40,
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MRM_F8 = 41, MRM_F9 = 42, MRM_D0 = 45, MRM_D1 = 46,
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MRM_D4 = 47, MRM_D5 = 48, MRM_D6 = 49, MRM_D8 = 50,
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MRM_D9 = 51, MRM_DA = 52, MRM_DB = 53, MRM_DC = 54,
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MRM_DD = 55, MRM_DE = 56, MRM_DF = 57,
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MRM_C8 = 37, MRM_C9 = 38, MRM_CA = 39, MRM_CB = 40,
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MRM_E8 = 41, MRM_F0 = 42, MRM_F8 = 45, MRM_F9 = 46,
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MRM_D0 = 47, MRM_D1 = 48, MRM_D4 = 49, MRM_D5 = 50,
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MRM_D6 = 51, MRM_D8 = 52, MRM_D9 = 53, MRM_DA = 54,
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MRM_DB = 55, MRM_DC = 56, MRM_DD = 57, MRM_DE = 58,
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MRM_DF = 59,
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/// RawFrmImm8 - This is used for the ENTER instruction, which has two
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/// immediates, the first of which is a 16-bit immediate (specified by
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@ -596,12 +597,13 @@ namespace X86II {
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}
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case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3:
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case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9:
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case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8:
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case X86II::MRM_F9: case X86II::MRM_D0: case X86II::MRM_D1:
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case X86II::MRM_D4: case X86II::MRM_D5: case X86II::MRM_D6:
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case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
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case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
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case X86II::MRM_DE: case X86II::MRM_DF:
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case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_E8:
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case X86II::MRM_F0: case X86II::MRM_F8: case X86II::MRM_F9:
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case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4:
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case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8:
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case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB:
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case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE:
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case X86II::MRM_DF:
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return -1;
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}
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}
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@ -1128,12 +1128,13 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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break;
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case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3:
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case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9:
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case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4:
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case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8:
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case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB:
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case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE:
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case X86II::MRM_DF: case X86II::MRM_E8: case X86II::MRM_F0:
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case X86II::MRM_F8: case X86II::MRM_F9:
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case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_D0:
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case X86II::MRM_D1: case X86II::MRM_D4: case X86II::MRM_D5:
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case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D9:
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case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC:
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case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF:
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case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8:
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case X86II::MRM_F9:
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EmitByte(BaseOpcode, CurByte, OS);
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unsigned char MRM;
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@ -1145,6 +1146,8 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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case X86II::MRM_C4: MRM = 0xC4; break;
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case X86II::MRM_C8: MRM = 0xC8; break;
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case X86II::MRM_C9: MRM = 0xC9; break;
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case X86II::MRM_CA: MRM = 0xCA; break;
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case X86II::MRM_CB: MRM = 0xCB; break;
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case X86II::MRM_D0: MRM = 0xD0; break;
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case X86II::MRM_D1: MRM = 0xD1; break;
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case X86II::MRM_D4: MRM = 0xD4; break;
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@ -1451,6 +1451,14 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
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MCE.emitByte(BaseOpcode);
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MCE.emitByte(0xC9);
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break;
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case X86II::MRM_CA:
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MCE.emitByte(BaseOpcode);
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MCE.emitByte(0xCA);
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break;
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case X86II::MRM_CB:
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MCE.emitByte(BaseOpcode);
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MCE.emitByte(0xCB);
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break;
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case X86II::MRM_E8:
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MCE.emitByte(BaseOpcode);
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MCE.emitByte(0xE8);
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@ -35,25 +35,27 @@ def MRM_C3 : Format<35>;
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def MRM_C4 : Format<36>;
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def MRM_C8 : Format<37>;
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def MRM_C9 : Format<38>;
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def MRM_E8 : Format<39>;
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def MRM_F0 : Format<40>;
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def MRM_F8 : Format<41>;
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def MRM_F9 : Format<42>;
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def MRM_CA : Format<39>;
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def MRM_CB : Format<40>;
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def MRM_E8 : Format<41>;
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def MRM_F0 : Format<42>;
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def RawFrmImm8 : Format<43>;
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def RawFrmImm16 : Format<44>;
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def MRM_D0 : Format<45>;
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def MRM_D1 : Format<46>;
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def MRM_D4 : Format<47>;
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def MRM_D5 : Format<48>;
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def MRM_D6 : Format<49>;
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def MRM_D8 : Format<50>;
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def MRM_D9 : Format<51>;
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def MRM_DA : Format<52>;
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def MRM_DB : Format<53>;
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def MRM_DC : Format<54>;
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def MRM_DD : Format<55>;
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def MRM_DE : Format<56>;
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def MRM_DF : Format<57>;
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def MRM_F8 : Format<45>;
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def MRM_F9 : Format<46>;
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def MRM_D0 : Format<47>;
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def MRM_D1 : Format<48>;
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def MRM_D4 : Format<49>;
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def MRM_D5 : Format<50>;
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def MRM_D6 : Format<51>;
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def MRM_D8 : Format<52>;
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def MRM_D9 : Format<53>;
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def MRM_DA : Format<54>;
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def MRM_DB : Format<55>;
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def MRM_DC : Format<56>;
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def MRM_DD : Format<57>;
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def MRM_DE : Format<58>;
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def MRM_DF : Format<59>;
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// ImmType - This specifies the immediate type used by an instruction. This is
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// part of the ad-hoc solution used to emit machine instruction encodings by our
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@ -520,3 +520,10 @@ def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
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def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
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"invpcid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
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Requires<[In64BitMode]>;
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//===----------------------------------------------------------------------===//
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// SMAP Instruction
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let Defs = [EFLAGS], Uses = [EFLAGS] in {
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def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
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def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
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}
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@ -121,3 +121,9 @@
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# CHECK: xsaveoptq (%rax)
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0x48 0x0f 0xae 0x30
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# CHECK: clac
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0x0f 0x01 0xca
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# CHECK: stac
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0x0f 0x01 0xcb
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@ -1228,3 +1228,11 @@ sysexitl
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// CHECK: sysexitq
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// CHECK: encoding: [0x48,0x0f,0x35]
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sysexitq
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// CHECK: clac
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// CHECK: encoding: [0x0f,0x01,0xca]
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clac
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// CHECK: stac
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// CHECK: encoding: [0x0f,0x01,0xcb]
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stac
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@ -29,23 +29,25 @@ using namespace llvm;
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MAP(C4, 36) \
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MAP(C8, 37) \
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MAP(C9, 38) \
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MAP(E8, 39) \
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MAP(F0, 40) \
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MAP(F8, 41) \
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MAP(F9, 42) \
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MAP(D0, 45) \
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MAP(D1, 46) \
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MAP(D4, 47) \
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MAP(D5, 48) \
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MAP(D6, 49) \
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MAP(D8, 50) \
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MAP(D9, 51) \
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MAP(DA, 52) \
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MAP(DB, 53) \
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MAP(DC, 54) \
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MAP(DD, 55) \
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MAP(DE, 56) \
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MAP(DF, 57)
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MAP(CA, 39) \
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MAP(CB, 40) \
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MAP(E8, 41) \
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MAP(F0, 42) \
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MAP(F8, 45) \
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MAP(F9, 46) \
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MAP(D0, 47) \
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MAP(D1, 48) \
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MAP(D4, 49) \
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MAP(D5, 50) \
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MAP(D6, 51) \
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MAP(D8, 52) \
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MAP(D9, 53) \
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MAP(DA, 54) \
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MAP(DB, 55) \
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MAP(DC, 56) \
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MAP(DD, 57) \
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MAP(DE, 58) \
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MAP(DF, 59)
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// A clone of X86 since we can't depend on something that is generated.
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namespace X86Local {
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