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Add a const and munge some comments

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216781 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reid Kleckner 2014-08-29 21:42:21 +00:00
parent 9436574d1b
commit 039f6c6ded
2 changed files with 6 additions and 4 deletions
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2
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
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@ -148,7 +148,7 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
// If we have a musttail call in a variadic funciton, we need to ensure we // If we have a musttail call in a variadic funciton, we need to ensure we
// forward implicit register parameters. // forward implicit register parameters.
if (auto *CI = dyn_cast<CallInst>(I)) { if (const auto *CI = dyn_cast<CallInst>(I)) {
if (CI->isMustTailCall() && Fn->isVarArg()) if (CI->isMustTailCall() && Fn->isVarArg())
MF->getFrameInfo()->setHasMustTailInVarArgFunc(true); MF->getFrameInfo()->setHasMustTailInVarArgFunc(true);
} }

8
lib/Target/X86/X86ISelLowering.cpp
View File

@ -2326,6 +2326,7 @@ X86TargetLowering::LowerMemArgument(SDValue Chain,
} }
} }
// FIXME: Get this from tablegen.
static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv, static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
const X86Subtarget *Subtarget) { const X86Subtarget *Subtarget) {
assert(Subtarget->is64Bit()); assert(Subtarget->is64Bit());
@ -2343,6 +2344,7 @@ static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
return GPR64ArgRegs64Bit; return GPR64ArgRegs64Bit;
} }
// FIXME: Get this from tablegen.
static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF, static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
CallingConv::ID CallConv, CallingConv::ID CallConv,
const X86Subtarget *Subtarget) { const X86Subtarget *Subtarget) {
@ -2351,6 +2353,7 @@ static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
// The XMM registers which might contain var arg parameters are shadowed // The XMM registers which might contain var arg parameters are shadowed
// in their paired GPR. So we only need to save the GPR to their home // in their paired GPR. So we only need to save the GPR to their home
// slots. // slots.
// TODO: __vectorcall will change this.
return None; return None;
} }
@ -2613,13 +2616,12 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
if (!MemOps.empty()) if (!MemOps.empty())
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
} else { } else {
// TODO: Save virtual registers away some where so we can do // Add all GPRs, al, and XMMs to the list of forwards. We will add then
// getCopyFromReg in the musttail call lowering bb. // to the liveout set on a musttail call.
assert(MFI->hasMustTailInVarArgFunc()); assert(MFI->hasMustTailInVarArgFunc());
auto &Forwards = FuncInfo->getForwardedMustTailRegParms(); auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
typedef X86MachineFunctionInfo::Forward Forward; typedef X86MachineFunctionInfo::Forward Forward;
// Add all GPRs, al, and XMMs to the list of forwards.
for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) { for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
unsigned VReg = unsigned VReg =
MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass); MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);