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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5302 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2003-01-15 19:47:53 +00:00
parent b66fdc2934
commit 0412077faf
4 changed files with 54 additions and 60 deletions
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20
lib/CodeGen/InstrSelection/InstrSelection.cpp
View File

@ -19,9 +19,12 @@
#include "llvm/Pass.h"
#include "Support/CommandLine.h"
#include "Support/LeakDetector.h"
using std::cerr;
using std::vector;
std::vector<MachineInstr*>
FixConstantOperandsForInstr(Instruction* vmInstr, MachineInstr* minstr,
TargetMachine& target);
namespace {
//===--------------------------------------------------------------------===//
// SelectDebugLevel - Allow command line control over debugging.
@ -108,10 +111,10 @@ bool InstructionSelection::runOnFunction(Function &F)
if (SelectDebugLevel >= Select_DebugInstTrees)
{
cerr << "\n\n*** Input to instruction selection for function "
<< F.getName() << "\n\n" << F
<< "\n\n*** Instruction trees for function "
<< F.getName() << "\n\n";
std::cerr << "\n\n*** Input to instruction selection for function "
<< F.getName() << "\n\n" << F
<< "\n\n*** Instruction trees for function "
<< F.getName() << "\n\n";
instrForest.dump();
}
@ -130,7 +133,7 @@ bool InstructionSelection::runOnFunction(Function &F)
if (SelectDebugLevel >= Select_DebugBurgTrees)
{
printcover(basicNode, 1, 0);
cerr << "\nCover cost == " << treecost(basicNode, 1, 0) << "\n\n";
std::cerr << "\nCover cost == " << treecost(basicNode, 1, 0) <<"\n\n";
printMatches(basicNode);
}
@ -159,7 +162,7 @@ bool InstructionSelection::runOnFunction(Function &F)
if (SelectDebugLevel >= Select_PrintMachineCode)
{
cerr << "\n*** Machine instructions after INSTRUCTION SELECTION\n";
std::cerr << "\n*** Machine instructions after INSTRUCTION SELECTION\n";
MachineFunction::get(&F).dump();
}
@ -276,7 +279,7 @@ InstructionSelection::SelectInstructionsForTree(InstrTreeNode* treeRoot,
int ruleForNode = burm_rule(treeRoot->state, goalnt);
if (ruleForNode == 0) {
cerr << "Could not match instruction tree for instr selection\n";
std::cerr << "Could not match instruction tree for instr selection\n";
abort();
}
@ -375,4 +378,3 @@ InstructionSelection::PostprocessMachineCodeForTree(InstructionNode* instrNode,
Pass *createInstructionSelectionPass(TargetMachine &T) {
return new InstructionSelection(T);
}

37
lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
View File

@ -298,8 +298,8 @@ GetMemInstArgs(InstructionNode* memInstrNode,
// If there are no indices, return the current pointer.
// Else extract the pointer from the GEP and fold the indices.
return (gepNode)? GetGEPInstArgs(gepNode, idxVec, allConstantIndices)
: ptrVal;
return gepNode ? GetGEPInstArgs(gepNode, idxVec, allConstantIndices)
: ptrVal;
}
MachineOperand::MachineOperandType
@ -380,6 +380,7 @@ ChooseRegOrImmed(Value* val,
}
//---------------------------------------------------------------------------
// Function: FixConstantOperandsForInstr
//
@ -400,7 +401,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
MachineInstr* minstr,
TargetMachine& target)
{
vector<MachineInstr*> loadConstVec;
vector<MachineInstr*> MVec;
MachineOpCode opCode = minstr->getOpCode();
const TargetInstrInfo& instrInfo = target.getInstrInfo();
@ -432,22 +433,18 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
if (mop.getType() == MachineOperand::MO_VirtualRegister)
{
assert(mop.getVRegValue() != NULL);
opValue = mop.getVRegValue();
if (Constant *opConst = dyn_cast<Constant>(opValue))
{
opType = ChooseRegOrImmed(opConst, opCode, target,
(immedPos == (int)op), machineRegNum, immedValue);
if (opType == MachineOperand::MO_VirtualRegister)
constantThatMustBeLoaded = true;
}
if (Constant *opConst = dyn_cast<Constant>(mop.getVRegValue())) {
opType = ChooseRegOrImmed(opConst, opCode, target,
(immedPos == (int)op), machineRegNum,
immedValue);
if (opType == MachineOperand::MO_VirtualRegister)
constantThatMustBeLoaded = true;
}
}
else
{
assert(mop.getType() == MachineOperand::MO_SignExtendedImmed ||
mop.getType() == MachineOperand::MO_UnextendedImmed);
bool isSigned = (mop.getType() ==
MachineOperand::MO_SignExtendedImmed);
assert(mop.isImmediate());
bool isSigned = mop.getType() == MachineOperand::MO_SignExtendedImmed;
// Bit-selection flags indicate an instruction that is extracting
// bits from its operand so ignore this even if it is a big constant.
@ -481,7 +478,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
{ // opValue is a constant that must be explicitly loaded into a reg
assert(opValue);
TmpInstruction* tmpReg = InsertCodeToLoadConstant(F, opValue, vmInstr,
loadConstVec, target);
MVec, target);
minstr->SetMachineOperandVal(op, MachineOperand::MO_VirtualRegister,
tmpReg);
}
@ -509,7 +506,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
{
Value* oldVal = minstr->getImplicitRef(i);
TmpInstruction* tmpReg =
InsertCodeToLoadConstant(F, oldVal, vmInstr, loadConstVec, target);
InsertCodeToLoadConstant(F, oldVal, vmInstr, MVec, target);
minstr->setImplicitRef(i, tmpReg);
if (isCall)
@ -524,7 +521,5 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
}
}
return loadConstVec;
return MVec;
}

20
lib/Target/SparcV9/InstrSelection/InstrSelection.cpp
View File

@ -19,9 +19,12 @@
#include "llvm/Pass.h"
#include "Support/CommandLine.h"
#include "Support/LeakDetector.h"
using std::cerr;
using std::vector;
std::vector<MachineInstr*>
FixConstantOperandsForInstr(Instruction* vmInstr, MachineInstr* minstr,
TargetMachine& target);
namespace {
//===--------------------------------------------------------------------===//
// SelectDebugLevel - Allow command line control over debugging.
@ -108,10 +111,10 @@ bool InstructionSelection::runOnFunction(Function &F)
if (SelectDebugLevel >= Select_DebugInstTrees)
{
cerr << "\n\n*** Input to instruction selection for function "
<< F.getName() << "\n\n" << F
<< "\n\n*** Instruction trees for function "
<< F.getName() << "\n\n";
std::cerr << "\n\n*** Input to instruction selection for function "
<< F.getName() << "\n\n" << F
<< "\n\n*** Instruction trees for function "
<< F.getName() << "\n\n";
instrForest.dump();
}
@ -130,7 +133,7 @@ bool InstructionSelection::runOnFunction(Function &F)
if (SelectDebugLevel >= Select_DebugBurgTrees)
{
printcover(basicNode, 1, 0);
cerr << "\nCover cost == " << treecost(basicNode, 1, 0) << "\n\n";
std::cerr << "\nCover cost == " << treecost(basicNode, 1, 0) <<"\n\n";
printMatches(basicNode);
}
@ -159,7 +162,7 @@ bool InstructionSelection::runOnFunction(Function &F)
if (SelectDebugLevel >= Select_PrintMachineCode)
{
cerr << "\n*** Machine instructions after INSTRUCTION SELECTION\n";
std::cerr << "\n*** Machine instructions after INSTRUCTION SELECTION\n";
MachineFunction::get(&F).dump();
}
@ -276,7 +279,7 @@ InstructionSelection::SelectInstructionsForTree(InstrTreeNode* treeRoot,
int ruleForNode = burm_rule(treeRoot->state, goalnt);
if (ruleForNode == 0) {
cerr << "Could not match instruction tree for instr selection\n";
std::cerr << "Could not match instruction tree for instr selection\n";
abort();
}
@ -375,4 +378,3 @@ InstructionSelection::PostprocessMachineCodeForTree(InstructionNode* instrNode,
Pass *createInstructionSelectionPass(TargetMachine &T) {
return new InstructionSelection(T);
}

37
lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
View File

@ -298,8 +298,8 @@ GetMemInstArgs(InstructionNode* memInstrNode,
// If there are no indices, return the current pointer.
// Else extract the pointer from the GEP and fold the indices.
return (gepNode)? GetGEPInstArgs(gepNode, idxVec, allConstantIndices)
: ptrVal;
return gepNode ? GetGEPInstArgs(gepNode, idxVec, allConstantIndices)
: ptrVal;
}
MachineOperand::MachineOperandType
@ -380,6 +380,7 @@ ChooseRegOrImmed(Value* val,
}
//---------------------------------------------------------------------------
// Function: FixConstantOperandsForInstr
//
@ -400,7 +401,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
MachineInstr* minstr,
TargetMachine& target)
{
vector<MachineInstr*> loadConstVec;
vector<MachineInstr*> MVec;
MachineOpCode opCode = minstr->getOpCode();
const TargetInstrInfo& instrInfo = target.getInstrInfo();
@ -432,22 +433,18 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
if (mop.getType() == MachineOperand::MO_VirtualRegister)
{
assert(mop.getVRegValue() != NULL);
opValue = mop.getVRegValue();
if (Constant *opConst = dyn_cast<Constant>(opValue))
{
opType = ChooseRegOrImmed(opConst, opCode, target,
(immedPos == (int)op), machineRegNum, immedValue);
if (opType == MachineOperand::MO_VirtualRegister)
constantThatMustBeLoaded = true;
}
if (Constant *opConst = dyn_cast<Constant>(mop.getVRegValue())) {
opType = ChooseRegOrImmed(opConst, opCode, target,
(immedPos == (int)op), machineRegNum,
immedValue);
if (opType == MachineOperand::MO_VirtualRegister)
constantThatMustBeLoaded = true;
}
}
else
{
assert(mop.getType() == MachineOperand::MO_SignExtendedImmed ||
mop.getType() == MachineOperand::MO_UnextendedImmed);
bool isSigned = (mop.getType() ==
MachineOperand::MO_SignExtendedImmed);
assert(mop.isImmediate());
bool isSigned = mop.getType() == MachineOperand::MO_SignExtendedImmed;
// Bit-selection flags indicate an instruction that is extracting
// bits from its operand so ignore this even if it is a big constant.
@ -481,7 +478,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
{ // opValue is a constant that must be explicitly loaded into a reg
assert(opValue);
TmpInstruction* tmpReg = InsertCodeToLoadConstant(F, opValue, vmInstr,
loadConstVec, target);
MVec, target);
minstr->SetMachineOperandVal(op, MachineOperand::MO_VirtualRegister,
tmpReg);
}
@ -509,7 +506,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
{
Value* oldVal = minstr->getImplicitRef(i);
TmpInstruction* tmpReg =
InsertCodeToLoadConstant(F, oldVal, vmInstr, loadConstVec, target);
InsertCodeToLoadConstant(F, oldVal, vmInstr, MVec, target);
minstr->setImplicitRef(i, tmpReg);
if (isCall)
@ -524,7 +521,5 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
}
}
return loadConstVec;
return MVec;
}