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[X86] Remove unnecessary WriteLEA InstRW overrides.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330648 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim 2018-04-23 21:04:23 +00:00
parent 04273076b9
commit 0597a75372
5 changed files with 5 additions and 16 deletions
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3
lib/Target/X86/X86SchedBroadwell.td
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@ -401,8 +401,7 @@ def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr", def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",
"BLSI(32|64)rr", "BLSI(32|64)rr",
"BLSMSK(32|64)rr", "BLSMSK(32|64)rr",
"BLSR(32|64)rr", "BLSR(32|64)rr")>;
"LEA(16|32|64)(_32)?r")>;
def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> { def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
let Latency = 1; let Latency = 1;

3
lib/Target/X86/X86SchedHaswell.td
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@ -745,8 +745,7 @@ def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {
def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr", def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr",
"BLSI(32|64)rr", "BLSI(32|64)rr",
"BLSMSK(32|64)rr", "BLSMSK(32|64)rr",
"BLSR(32|64)rr", "BLSR(32|64)rr")>;
"LEA(16|32|64)(_32)?r")>;
def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> { def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {
let Latency = 1; let Latency = 1;

9
lib/Target/X86/X86SchedSandyBridge.td
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@ -120,7 +120,7 @@ def : WriteRes<WriteSETCCStore, [SBPort05,SBPort4,SBPort23]> {
// This is for simple LEAs with one or two input operands. // This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on // The complex ones can only execute on port 1, and they require two cycles on
// the port to read all inputs. We don't model that. // the port to read all inputs. We don't model that.
def : WriteRes<WriteLEA, [SBPort15]>; def : WriteRes<WriteLEA, [SBPort01]>;
// Bit counts. // Bit counts.
defm : SBWriteResPair<WriteBitScan, [SBPort1], 3, [1], 1, 5>; defm : SBWriteResPair<WriteBitScan, [SBPort1], 3, [1], 1, 5>;
@ -341,13 +341,6 @@ def: InstRW<[SBWriteResGroup2], (instregex "FFREE",
"(V?)MOV64toPQIrr", "(V?)MOV64toPQIrr",
"(V?)MOVDI2PDIrr")>; "(V?)MOVDI2PDIrr")>;
def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> {
let Latency = 1;
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup3], (instregex "LEA(16|32|64)(_32)?r")>;
def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> { def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
let Latency = 1; let Latency = 1;
let NumMicroOps = 1; let NumMicroOps = 1;

3
lib/Target/X86/X86SchedSkylakeClient.td
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@ -485,8 +485,7 @@ def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr", def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr",
"BLSI(32|64)rr", "BLSI(32|64)rr",
"BLSMSK(32|64)rr", "BLSMSK(32|64)rr",
"BLSR(32|64)rr", "BLSR(32|64)rr")>;
"LEA(16|32|64)(_32)?r")>;
def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> { def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
let Latency = 1; let Latency = 1;

3
lib/Target/X86/X86SchedSkylakeServer.td
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@ -790,8 +790,7 @@ def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr", def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr",
"BLSI(32|64)rr", "BLSI(32|64)rr",
"BLSMSK(32|64)rr", "BLSMSK(32|64)rr",
"BLSR(32|64)rr", "BLSR(32|64)rr")>;
"LEA(16|32|64)(_32)?r")>;
def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> { def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
let Latency = 1; let Latency = 1;